]>
Commit | Line | Data |
---|---|---|
e874a669 EL |
1 | Device Tree Clock bindings for arch-sunxi |
2 | ||
3 | This binding uses the common clock binding[1]. | |
4 | ||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
6 | ||
7 | Required properties: | |
8 | - compatible : shall be one of the following: | |
9 | "allwinner,sunxi-osc-clk" - for a gatable oscillator | |
10 | "allwinner,sunxi-pll1-clk" - for the main PLL clock | |
11 | "allwinner,sunxi-cpu-clk" - for the CPU multiplexer clock | |
12 | "allwinner,sunxi-axi-clk" - for the sunxi AXI clock | |
13 | "allwinner,sunxi-ahb-clk" - for the sunxi AHB clock | |
14 | "allwinner,sunxi-apb0-clk" - for the sunxi APB0 clock | |
15 | "allwinner,sunxi-apb1-clk" - for the sunxi APB1 clock | |
16 | "allwinner,sunxi-apb1-mux-clk" - for the sunxi APB1 clock muxing | |
17 | ||
18 | Required properties for all clocks: | |
19 | - reg : shall be the control register address for the clock. | |
20 | - clocks : shall be the input parent clock(s) phandle for the clock | |
21 | - #clock-cells : from common clock binding; shall be set to 0. | |
22 | ||
23 | For example: | |
24 | ||
25 | osc24M: osc24M@01c20050 { | |
26 | #clock-cells = <0>; | |
27 | compatible = "allwinner,sunxi-osc-clk"; | |
28 | reg = <0x01c20050 0x4>; | |
29 | clocks = <&osc24M_fixed>; | |
30 | }; | |
31 | ||
32 | pll1: pll1@01c20000 { | |
33 | #clock-cells = <0>; | |
34 | compatible = "allwinner,sunxi-pll1-clk"; | |
35 | reg = <0x01c20000 0x4>; | |
36 | clocks = <&osc24M>; | |
37 | }; | |
38 | ||
39 | cpu: cpu@01c20054 { | |
40 | #clock-cells = <0>; | |
41 | compatible = "allwinner,sunxi-cpu-clk"; | |
42 | reg = <0x01c20054 0x4>; | |
43 | clocks = <&osc32k>, <&osc24M>, <&pll1>; | |
44 | }; |