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dt-bindings: display: meson-vpu: Add missing amlogic,canvas property
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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Amlogic Meson Display Controller
9
10maintainers:
11 - Neil Armstrong <narmstrong@baylibre.com>
12
13description: |
14 The Amlogic Meson Display controller is composed of several components
15 that are going to be documented below
16
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
18 | vd1 _______ _____________ _________________ | |
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
23 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
24 A | osd1 | | | Blenders | | Encl ----------|----|---------------|
25 M |-------|______|----|____________| |________________| | |
26 ___|__________________________________________________________|_______________|
27
28
29 VIU: Video Input Unit
30 ---------------------
31
32 The Video Input Unit is in charge of the pixel scanout from the DDR memory.
33 It fetches the frames addresses, stride and parameters from the "Canvas" memory.
34 This part is also in charge of the CSC (Colorspace Conversion).
35 It can handle 2 OSD Planes and 2 Video Planes.
36
37 VPP: Video Post Processing
38 --------------------------
39
40 The Video Post Processing is in charge of the scaling and blending of the
41 various planes into a single pixel stream.
42 There is a special "pre-blending" used by the video planes with a dedicated
43 scaler and a "post-blending" to merge with the OSD Planes.
44 The OSD planes also have a dedicated scaler for one of the OSD.
45
46 VENC: Video Encoders
47 --------------------
48
49 The VENC is composed of the multiple pixel encoders
50 - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
51 - ENCP : Progressive Video Encoder for HDMI
52 - ENCL : LCD LVDS Encoder
53 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
54 tree and provides the scanout clock to the VPP and VIU.
55 The ENCI is connected to a single VDAC for Composite Output.
56 The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
57
58properties:
59 compatible:
60 oneOf:
61 - items:
62 - enum:
63 - amlogic,meson-gxbb-vpu # GXBB (S905)
64 - amlogic,meson-gxl-vpu # GXL (S905X, S905D)
65 - amlogic,meson-gxm-vpu # GXM (S912)
66 - const: amlogic,meson-gx-vpu
67 - enum:
68 - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
69
70 reg:
71 maxItems: 2
72
73 reg-names:
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74 items:
75 - const: vpu
76 - const: hhi
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77
78 interrupts:
79 maxItems: 1
80
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81 amlogic,canvas:
82 description: should point to a canvas provider node
83 $ref: /schemas/types.yaml#/definitions/phandle
84
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85 power-domains:
86 maxItems: 1
87 description: phandle to the associated power domain
88
89 port@0:
b6755423 90 $ref: /schemas/graph.yaml#/properties/port
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91 description:
92 A port node pointing to the CVBS VDAC port node.
93
94 port@1:
b6755423 95 $ref: /schemas/graph.yaml#/properties/port
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96 description:
97 A port node pointing to the HDMI-TX port node.
98
99 "#address-cells":
100 const: 1
101
102 "#size-cells":
103 const: 0
104
105required:
106 - compatible
107 - reg
108 - interrupts
109 - port@0
110 - port@1
111 - "#address-cells"
112 - "#size-cells"
2599434f 113 - amlogic,canvas
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115additionalProperties: false
116
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117examples:
118 - |
119 vpu: vpu@d0100000 {
120 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
121 reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;
122 reg-names = "vpu", "hhi";
123 interrupts = <3>;
124 #address-cells = <1>;
125 #size-cells = <0>;
2599434f 126 amlogic,canvas = <&canvas>;
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127
128 /* CVBS VDAC output port */
129 port@0 {
130 reg = <0>;
131
132 cvbs_vdac_out: endpoint {
133 remote-endpoint = <&tv_connector_in>;
134 };
135 };
136
137 /* HDMI TX output port */
138 port@1 {
139 reg = <1>;
140
141 hdmi_tx_out: endpoint {
142 remote-endpoint = <&hdmi_tx_in>;
143 };
144 };
145 };