]>
Commit | Line | Data |
---|---|---|
ac4c1a9b SH |
1 | Device-Tree bindings for LVDS Display Bridge (ldb) |
2 | ||
3 | LVDS Display Bridge | |
4 | =================== | |
5 | ||
6 | The LVDS Display Bridge device tree node contains up to two lvds-channel | |
7 | nodes describing each of the two LVDS encoder channels of the bridge. | |
8 | ||
9 | Required properties: | |
10 | - #address-cells : should be <1> | |
11 | - #size-cells : should be <0> | |
12 | - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". | |
13 | Both LDB versions are similar, but i.MX6 has an additional | |
14 | multiplexer in the front to select any of the four IPU display | |
15 | interfaces as input for each LVDS channel. | |
16 | - gpr : should be <&gpr> on i.MX53 and i.MX6q. | |
17 | The phandle points to the iomuxc-gpr region containing the LVDS | |
18 | control register. | |
19 | - clocks, clock-names : phandles to the LDB divider and selector clocks and to | |
20 | the display interface selector clocks, as described in | |
21 | Documentation/devicetree/bindings/clock/clock-bindings.txt | |
22 | The following clocks are expected on i.MX53: | |
23 | "di0_pll" - LDB LVDS channel 0 mux | |
24 | "di1_pll" - LDB LVDS channel 1 mux | |
25 | "di0" - LDB LVDS channel 0 gate | |
26 | "di1" - LDB LVDS channel 1 gate | |
27 | "di0_sel" - IPU1 DI0 mux | |
28 | "di1_sel" - IPU1 DI1 mux | |
29 | On i.MX6q the following additional clocks are needed: | |
30 | "di2_sel" - IPU2 DI0 mux | |
31 | "di3_sel" - IPU2 DI1 mux | |
32 | The needed clock numbers for each are documented in | |
33 | Documentation/devicetree/bindings/clock/imx5-clock.txt, and in | |
34 | Documentation/devicetree/bindings/clock/imx6q-clock.txt. | |
35 | ||
36 | Optional properties: | |
37 | - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q | |
38 | - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, | |
39 | not used on i.MX6q | |
40 | - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should | |
41 | be configured - one input will be distributed on both outputs in dual | |
42 | channel mode | |
43 | ||
44 | LVDS Channel | |
45 | ============ | |
46 | ||
751e2676 PZ |
47 | Each LVDS Channel has to contain either an of graph link to a panel device node |
48 | or a display-timings node that describes the video timings for the connected | |
49 | LVDS display as well as the fsl,data-mapping and fsl,data-width properties. | |
ac4c1a9b SH |
50 | |
51 | Required properties: | |
52 | - reg : should be <0> or <1> | |
751e2676 PZ |
53 | - port: Input and output port nodes with endpoint definitions as defined in |
54 | Documentation/devicetree/bindings/graph.txt. | |
55 | On i.MX5, the internal two-input-multiplexer is used. Due to hardware | |
56 | limitations, only one input port (port@[0,1]) can be used for each channel | |
57 | (lvds-channel@[0,1], respectively). | |
58 | On i.MX6, there should be four input ports (port@[0-3]) that correspond | |
59 | to the four LVDS multiplexer inputs. | |
60 | A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected | |
61 | to a panel input port. Optionally, the output port can be left out if | |
62 | display-timings are used instead. | |
63 | ||
64 | Optional properties (required if display-timings are used): | |
ee896866 | 65 | - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing |
751e2676 | 66 | - display-timings : A node that describes the display timings as defined in |
75640e79 | 67 | Documentation/devicetree/bindings/display/panel/display-timing.txt. |
ac4c1a9b SH |
68 | - fsl,data-mapping : should be "spwg" or "jeida" |
69 | This describes how the color bits are laid out in the | |
70 | serialized LVDS signal. | |
71 | - fsl,data-width : should be <18> or <24> | |
72 | ||
73 | example: | |
74 | ||
75 | gpr: iomuxc-gpr@53fa8000 { | |
76 | /* ... */ | |
77 | }; | |
78 | ||
79 | ldb: ldb@53fa8008 { | |
80 | #address-cells = <1>; | |
81 | #size-cells = <0>; | |
82 | compatible = "fsl,imx53-ldb"; | |
83 | gpr = <&gpr>; | |
751e2676 PZ |
84 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
85 | <&clks IMX5_CLK_LDB_DI1_SEL>, | |
86 | <&clks IMX5_CLK_IPU_DI0_SEL>, | |
87 | <&clks IMX5_CLK_IPU_DI1_SEL>, | |
88 | <&clks IMX5_CLK_LDB_DI0_GATE>, | |
89 | <&clks IMX5_CLK_LDB_DI1_GATE>; | |
ac4c1a9b SH |
90 | clock-names = "di0_pll", "di1_pll", |
91 | "di0_sel", "di1_sel", | |
92 | "di0", "di1"; | |
93 | ||
751e2676 | 94 | /* Using an of-graph endpoint link to connect the panel */ |
ac4c1a9b | 95 | lvds-channel@0 { |
1b134c9c MN |
96 | #address-cells = <1>; |
97 | #size-cells = <0>; | |
ac4c1a9b | 98 | reg = <0>; |
408eb4f5 | 99 | |
1b134c9c MN |
100 | port@0 { |
101 | reg = <0>; | |
102 | ||
408eb4f5 PZ |
103 | lvds0_in: endpoint { |
104 | remote-endpoint = <&ipu_di0_lvds0>; | |
105 | }; | |
106 | }; | |
751e2676 PZ |
107 | |
108 | port@2 { | |
109 | reg = <2>; | |
110 | ||
111 | lvds0_out: endpoint { | |
112 | remote-endpoint = <&panel_in>; | |
113 | }; | |
114 | }; | |
ac4c1a9b SH |
115 | }; |
116 | ||
751e2676 | 117 | /* Using display-timings and fsl,data-mapping/width instead */ |
ac4c1a9b | 118 | lvds-channel@1 { |
1b134c9c MN |
119 | #address-cells = <1>; |
120 | #size-cells = <0>; | |
ac4c1a9b | 121 | reg = <1>; |
ac4c1a9b SH |
122 | fsl,data-mapping = "spwg"; |
123 | fsl,data-width = <24>; | |
124 | ||
125 | display-timings { | |
126 | /* ... */ | |
127 | }; | |
408eb4f5 | 128 | |
1b134c9c MN |
129 | port@1 { |
130 | reg = <1>; | |
131 | ||
408eb4f5 PZ |
132 | lvds1_in: endpoint { |
133 | remote-endpoint = <&ipu_di1_lvds1>; | |
134 | }; | |
135 | }; | |
ac4c1a9b SH |
136 | }; |
137 | }; | |
751e2676 PZ |
138 | |
139 | panel: lvds-panel { | |
140 | /* ... */ | |
141 | ||
142 | port { | |
143 | panel_in: endpoint { | |
144 | remote-endpoint = <&lvds0_out>; | |
145 | }; | |
146 | }; | |
147 | }; |