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Commit | Line | Data |
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01f8c951 LP |
1 | Rockchip DWC HDMI TX Encoder |
2 | ============================ | |
3 | ||
4 | The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP | |
5 | with a companion PHY IP. | |
6 | ||
7 | These DT bindings follow the Synopsys DWC HDMI TX bindings defined in | |
8 | Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the | |
9 | following device-specific properties. | |
10 | ||
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11 | |
12 | Required properties: | |
01f8c951 | 13 | |
6445e394 MY |
14 | - compatible: should be one of the following: |
15 | "rockchip,rk3288-dw-hdmi" | |
16 | "rockchip,rk3399-dw-hdmi" | |
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17 | - reg: See dw_hdmi.txt. |
18 | - reg-io-width: See dw_hdmi.txt. Shall be 4. | |
74af9e4d | 19 | - interrupts: HDMI interrupt number |
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20 | - clocks: See dw_hdmi.txt. |
21 | - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. | |
22 | - ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0 | |
23 | corresponding to the video input of the controller. The port shall have two | |
24 | endpoints, numbered 0 and 1, connected respectively to the vopb and vopl. | |
25 | - rockchip,grf: Shall reference the GRF to mux vopl/vopb. | |
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26 | |
27 | Optional properties | |
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28 | |
29 | - ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master | |
30 | or the functionally-reduced I2C master contained in the DWC HDMI. When | |
31 | connected to a system I2C master this property contains a phandle to that | |
32 | I2C master controller. | |
33 | - clock-names: See dw_hdmi.txt. The "cec" clock is optional. | |
34 | - clock-names: May contain "cec" as defined in dw_hdmi.txt. | |
8814b40b | 35 | - clock-names: May contain "grf", power for grf io. |
5e3bc6d1 | 36 | - clock-names: May contain "vpll", external clock for some hdmi phy. |
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37 | |
38 | Example: | |
01f8c951 | 39 | |
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40 | hdmi: hdmi@ff980000 { |
41 | compatible = "rockchip,rk3288-dw-hdmi"; | |
42 | reg = <0xff980000 0x20000>; | |
43 | reg-io-width = <4>; | |
44 | ddc-i2c-bus = <&i2c5>; | |
45 | rockchip,grf = <&grf>; | |
46 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
47 | clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; | |
48 | clock-names = "iahb", "isfr"; | |
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49 | ports { |
50 | hdmi_in: port { | |
51 | #address-cells = <1>; | |
52 | #size-cells = <0>; | |
53 | hdmi_in_vopb: endpoint@0 { | |
54 | reg = <0>; | |
55 | remote-endpoint = <&vopb_out_hdmi>; | |
56 | }; | |
57 | hdmi_in_vopl: endpoint@1 { | |
58 | reg = <1>; | |
59 | remote-endpoint = <&vopl_out_hdmi>; | |
60 | }; | |
61 | }; | |
62 | }; | |
63 | }; |