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21a454fd MR |
1 | Allwinner A10 Display Pipeline |
2 | ============================== | |
3 | ||
4 | The Allwinner A10 Display pipeline is composed of several components | |
5 | that are going to be documented below: | |
6 | ||
9181b5bb CYT |
7 | For all connections between components up to the TCONs in the display |
8 | pipeline, when there are multiple components of the same type at the | |
9 | same depth, the local endpoint ID must be the same as the remote | |
10 | component's index. For example, if the remote endpoint is Frontend 1, | |
11 | then the local endpoint ID must be 1. | |
12 | ||
13 | Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0 | |
14 | [1] -- -- [1] [1] -- -- [1] | |
15 | \ / \ / | |
16 | X X | |
17 | / \ / \ | |
18 | [0] -- -- [0] [0] -- -- [0] | |
19 | Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1 | |
20 | ||
21 | For a two pipeline system such as the one depicted above, the lines | |
22 | represent the connections between the components, while the numbers | |
23 | within the square brackets corresponds to the ID of the local endpoint. | |
24 | ||
25 | The same rule also applies to DE 2.0 mixer-TCON connections: | |
26 | ||
27 | Mixer 0 [0] ----------- [0] TCON 0 | |
28 | [1] ---- ---- [1] | |
29 | \ / | |
30 | X | |
31 | / \ | |
32 | [0] ---- ---- [0] | |
33 | Mixer 1 [1] ----------- [1] TCON 1 | |
de120d09 | 34 | |
1240f0b9 MR |
35 | HDMI Encoder |
36 | ------------ | |
37 | ||
38 | The HDMI Encoder supports the HDMI video and audio outputs, and does | |
39 | CEC. It is one end of the pipeline. | |
40 | ||
41 | Required properties: | |
42 | - compatible: value must be one of: | |
43 | * allwinner,sun5i-a10s-hdmi | |
44 | - reg: base address and size of memory-mapped region | |
45 | - interrupts: interrupt associated to this IP | |
46 | - clocks: phandles to the clocks feeding the HDMI encoder | |
47 | * ahb: the HDMI interface clock | |
48 | * mod: the HDMI module clock | |
49 | * pll-0: the first video PLL | |
50 | * pll-1: the second video PLL | |
51 | - clock-names: the clock names mentioned above | |
52 | - dmas: phandles to the DMA channels used by the HDMI encoder | |
53 | * ddc-tx: The channel for DDC transmission | |
54 | * ddc-rx: The channel for DDC reception | |
55 | * audio-tx: The channel used for audio transmission | |
56 | - dma-names: the channel names mentioned above | |
57 | ||
58 | - ports: A ports node with endpoint definitions as defined in | |
59 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
60 | first port should be the input endpoint. The second should be the | |
61 | output, usually to an HDMI connector. | |
62 | ||
21a454fd MR |
63 | TV Encoder |
64 | ---------- | |
65 | ||
66 | The TV Encoder supports the composite and VGA output. It is one end of | |
67 | the pipeline. | |
68 | ||
69 | Required properties: | |
70 | - compatible: value should be "allwinner,sun4i-a10-tv-encoder". | |
71 | - reg: base address and size of memory-mapped region | |
72 | - clocks: the clocks driving the TV encoder | |
73 | - resets: phandle to the reset controller driving the encoder | |
74 | ||
75 | - ports: A ports node with endpoint definitions as defined in | |
76 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
77 | first port should be the input endpoint. | |
78 | ||
79 | TCON | |
80 | ---- | |
81 | ||
82 | The TCON acts as a timing controller for RGB, LVDS and TV interfaces. | |
83 | ||
84 | Required properties: | |
4a408f1f MR |
85 | - compatible: value must be either: |
86 | * allwinner,sun5i-a13-tcon | |
93a5ec14 CYT |
87 | * allwinner,sun6i-a31-tcon |
88 | * allwinner,sun6i-a31s-tcon | |
4a408f1f | 89 | * allwinner,sun8i-a33-tcon |
f23c68a9 | 90 | * allwinner,sun8i-v3s-tcon |
21a454fd MR |
91 | - reg: base address and size of memory-mapped region |
92 | - interrupts: interrupt associated to this IP | |
93 | - clocks: phandles to the clocks feeding the TCON. Three are needed: | |
94 | - 'ahb': the interface clocks | |
95 | - 'tcon-ch0': The clock driving the TCON channel 0 | |
21a454fd MR |
96 | - resets: phandles to the reset controllers driving the encoder |
97 | - "lcd": the reset line for the TCON channel 0 | |
98 | ||
99 | - clock-names: the clock names mentioned above | |
100 | - reset-names: the reset names mentioned above | |
101 | - clock-output-names: Name of the pixel clock created | |
102 | ||
103 | - ports: A ports node with endpoint definitions as defined in | |
104 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
105 | first port should be the input endpoint, the second one the output | |
106 | ||
22662f12 MR |
107 | The output may have multiple endpoints. The TCON has two channels, |
108 | usually with the first channel being used for the panels interfaces | |
109 | (RGB, LVDS, etc.), and the second being used for the outputs that | |
110 | require another controller (TV Encoder, HDMI, etc.). The endpoints | |
111 | will take an extra property, allwinner,tcon-channel, to specify the | |
112 | channel the endpoint is associated to. If that property is not | |
113 | present, the endpoint number will be used as the channel number. | |
21a454fd | 114 | |
f23c68a9 | 115 | On SoCs other than the A33 and V3s, there is one more clock required: |
4a408f1f MR |
116 | - 'tcon-ch1': The clock driving the TCON channel 1 |
117 | ||
cd8fff50 MR |
118 | DRC |
119 | --- | |
120 | ||
121 | The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs | |
122 | (A31, A23, A33), allows to dynamically adjust pixel | |
123 | brightness/contrast based on histogram measurements for LCD content | |
124 | adaptive backlight control. | |
125 | ||
126 | ||
127 | Required properties: | |
128 | - compatible: value must be one of: | |
b3e0b2db CYT |
129 | * allwinner,sun6i-a31-drc |
130 | * allwinner,sun6i-a31s-drc | |
cd8fff50 MR |
131 | * allwinner,sun8i-a33-drc |
132 | - reg: base address and size of the memory-mapped region. | |
133 | - interrupts: interrupt associated to this IP | |
134 | - clocks: phandles to the clocks feeding the DRC | |
135 | * ahb: the DRC interface clock | |
136 | * mod: the DRC module clock | |
137 | * ram: the DRC DRAM clock | |
138 | - clock-names: the clock names mentioned above | |
139 | - resets: phandles to the reset line driving the DRC | |
140 | ||
141 | - ports: A ports node with endpoint definitions as defined in | |
142 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
143 | first port should be the input endpoints, the second one the outputs | |
21a454fd MR |
144 | |
145 | Display Engine Backend | |
146 | ---------------------- | |
147 | ||
148 | The display engine backend exposes layers and sprites to the | |
149 | system. | |
150 | ||
151 | Required properties: | |
152 | - compatible: value must be one of: | |
153 | * allwinner,sun5i-a13-display-backend | |
49c440e8 | 154 | * allwinner,sun6i-a31-display-backend |
4a408f1f | 155 | * allwinner,sun8i-a33-display-backend |
21a454fd | 156 | - reg: base address and size of the memory-mapped region. |
9904e70a | 157 | - interrupts: interrupt associated to this IP |
21a454fd MR |
158 | - clocks: phandles to the clocks feeding the frontend and backend |
159 | * ahb: the backend interface clock | |
160 | * mod: the backend module clock | |
161 | * ram: the backend DRAM clock | |
162 | - clock-names: the clock names mentioned above | |
163 | - resets: phandles to the reset controllers driving the backend | |
164 | ||
165 | - ports: A ports node with endpoint definitions as defined in | |
166 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
167 | first port should be the input endpoints, the second one the output | |
168 | ||
440d2c7b MR |
169 | On the A33, some additional properties are required: |
170 | - reg needs to have an additional region corresponding to the SAT | |
171 | - reg-names need to be set, with "be" and "sat" | |
172 | - clocks and clock-names need to have a phandle to the SAT bus | |
173 | clocks, whose name will be "sat" | |
174 | - resets and reset-names need to have a phandle to the SAT bus | |
175 | resets, whose name will be "sat" | |
176 | ||
21a454fd MR |
177 | Display Engine Frontend |
178 | ----------------------- | |
179 | ||
180 | The display engine frontend does formats conversion, scaling, | |
181 | deinterlacing and color space conversion. | |
182 | ||
183 | Required properties: | |
184 | - compatible: value must be one of: | |
185 | * allwinner,sun5i-a13-display-frontend | |
49c440e8 | 186 | * allwinner,sun6i-a31-display-frontend |
4a408f1f | 187 | * allwinner,sun8i-a33-display-frontend |
21a454fd MR |
188 | - reg: base address and size of the memory-mapped region. |
189 | - interrupts: interrupt associated to this IP | |
190 | - clocks: phandles to the clocks feeding the frontend and backend | |
191 | * ahb: the backend interface clock | |
192 | * mod: the backend module clock | |
193 | * ram: the backend DRAM clock | |
194 | - clock-names: the clock names mentioned above | |
195 | - resets: phandles to the reset controllers driving the backend | |
196 | ||
197 | - ports: A ports node with endpoint definitions as defined in | |
198 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
199 | first port should be the input endpoints, the second one the outputs | |
200 | ||
f23c68a9 IZ |
201 | Display Engine 2.0 Mixer |
202 | ------------------------ | |
203 | ||
204 | The DE2 mixer have many functionalities, currently only layer blending is | |
205 | supported. | |
206 | ||
207 | Required properties: | |
208 | - compatible: value must be one of: | |
209 | * allwinner,sun8i-v3s-de2-mixer | |
210 | - reg: base address and size of the memory-mapped region. | |
211 | - clocks: phandles to the clocks feeding the mixer | |
212 | * bus: the mixer interface clock | |
213 | * mod: the mixer module clock | |
214 | - clock-names: the clock names mentioned above | |
215 | - resets: phandles to the reset controllers driving the mixer | |
216 | ||
217 | - ports: A ports node with endpoint definitions as defined in | |
218 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
219 | first port should be the input endpoints, the second one the output | |
220 | ||
21a454fd MR |
221 | |
222 | Display Engine Pipeline | |
223 | ----------------------- | |
224 | ||
225 | The display engine pipeline (and its entry point, since it can be | |
226 | either directly the backend or the frontend) is represented as an | |
227 | extra node. | |
228 | ||
229 | Required properties: | |
230 | - compatible: value must be one of: | |
110d33dd | 231 | * allwinner,sun5i-a10s-display-engine |
21a454fd | 232 | * allwinner,sun5i-a13-display-engine |
49c440e8 CYT |
233 | * allwinner,sun6i-a31-display-engine |
234 | * allwinner,sun6i-a31s-display-engine | |
4a408f1f | 235 | * allwinner,sun8i-a33-display-engine |
f23c68a9 | 236 | * allwinner,sun8i-v3s-display-engine |
21a454fd MR |
237 | |
238 | - allwinner,pipelines: list of phandle to the display engine | |
f23c68a9 | 239 | frontends (DE 1.0) or mixers (DE 2.0) available. |
21a454fd MR |
240 | |
241 | Example: | |
242 | ||
243 | panel: panel { | |
244 | compatible = "olimex,lcd-olinuxino-43-ts"; | |
245 | #address-cells = <1>; | |
246 | #size-cells = <0>; | |
247 | ||
248 | port { | |
249 | #address-cells = <1>; | |
250 | #size-cells = <0>; | |
251 | ||
252 | panel_input: endpoint { | |
253 | remote-endpoint = <&tcon0_out_panel>; | |
254 | }; | |
255 | }; | |
256 | }; | |
257 | ||
1240f0b9 MR |
258 | connector { |
259 | compatible = "hdmi-connector"; | |
260 | type = "a"; | |
261 | ||
262 | port { | |
263 | hdmi_con_in: endpoint { | |
264 | remote-endpoint = <&hdmi_out_con>; | |
265 | }; | |
266 | }; | |
267 | }; | |
268 | ||
48c926cd | 269 | hdmi: hdmi@1c16000 { |
1240f0b9 MR |
270 | compatible = "allwinner,sun5i-a10s-hdmi"; |
271 | reg = <0x01c16000 0x1000>; | |
272 | interrupts = <58>; | |
273 | clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, | |
274 | <&ccu CLK_PLL_VIDEO0_2X>, | |
275 | <&ccu CLK_PLL_VIDEO1_2X>; | |
276 | clock-names = "ahb", "mod", "pll-0", "pll-1"; | |
277 | dmas = <&dma SUN4I_DMA_NORMAL 16>, | |
278 | <&dma SUN4I_DMA_NORMAL 16>, | |
279 | <&dma SUN4I_DMA_DEDICATED 24>; | |
280 | dma-names = "ddc-tx", "ddc-rx", "audio-tx"; | |
1240f0b9 MR |
281 | |
282 | ports { | |
283 | #address-cells = <1>; | |
284 | #size-cells = <0>; | |
285 | ||
286 | port@0 { | |
287 | #address-cells = <1>; | |
288 | #size-cells = <0>; | |
289 | reg = <0>; | |
290 | ||
291 | hdmi_in_tcon0: endpoint { | |
292 | remote-endpoint = <&tcon0_out_hdmi>; | |
293 | }; | |
294 | }; | |
295 | ||
296 | port@1 { | |
297 | #address-cells = <1>; | |
298 | #size-cells = <0>; | |
299 | reg = <1>; | |
300 | ||
301 | hdmi_out_con: endpoint { | |
302 | remote-endpoint = <&hdmi_con_in>; | |
303 | }; | |
304 | }; | |
305 | }; | |
306 | }; | |
307 | ||
48c926cd | 308 | tve0: tv-encoder@1c0a000 { |
21a454fd MR |
309 | compatible = "allwinner,sun4i-a10-tv-encoder"; |
310 | reg = <0x01c0a000 0x1000>; | |
311 | clocks = <&ahb_gates 34>; | |
312 | resets = <&tcon_ch0_clk 0>; | |
313 | ||
314 | port { | |
315 | #address-cells = <1>; | |
316 | #size-cells = <0>; | |
317 | ||
318 | tve0_in_tcon0: endpoint@0 { | |
319 | reg = <0>; | |
320 | remote-endpoint = <&tcon0_out_tve0>; | |
321 | }; | |
322 | }; | |
323 | }; | |
324 | ||
325 | tcon0: lcd-controller@1c0c000 { | |
326 | compatible = "allwinner,sun5i-a13-tcon"; | |
327 | reg = <0x01c0c000 0x1000>; | |
328 | interrupts = <44>; | |
329 | resets = <&tcon_ch0_clk 1>; | |
330 | reset-names = "lcd"; | |
331 | clocks = <&ahb_gates 36>, | |
332 | <&tcon_ch0_clk>, | |
333 | <&tcon_ch1_clk>; | |
334 | clock-names = "ahb", | |
335 | "tcon-ch0", | |
336 | "tcon-ch1"; | |
337 | clock-output-names = "tcon-pixel-clock"; | |
338 | ||
339 | ports { | |
340 | #address-cells = <1>; | |
341 | #size-cells = <0>; | |
342 | ||
343 | tcon0_in: port@0 { | |
344 | #address-cells = <1>; | |
345 | #size-cells = <0>; | |
346 | reg = <0>; | |
347 | ||
348 | tcon0_in_be0: endpoint@0 { | |
349 | reg = <0>; | |
350 | remote-endpoint = <&be0_out_tcon0>; | |
351 | }; | |
352 | }; | |
353 | ||
354 | tcon0_out: port@1 { | |
355 | #address-cells = <1>; | |
356 | #size-cells = <0>; | |
357 | reg = <1>; | |
358 | ||
359 | tcon0_out_panel: endpoint@0 { | |
360 | reg = <0>; | |
361 | remote-endpoint = <&panel_input>; | |
362 | }; | |
363 | ||
364 | tcon0_out_tve0: endpoint@1 { | |
365 | reg = <1>; | |
366 | remote-endpoint = <&tve0_in_tcon0>; | |
367 | }; | |
368 | }; | |
369 | }; | |
370 | }; | |
371 | ||
372 | fe0: display-frontend@1e00000 { | |
373 | compatible = "allwinner,sun5i-a13-display-frontend"; | |
374 | reg = <0x01e00000 0x20000>; | |
375 | interrupts = <47>; | |
376 | clocks = <&ahb_gates 46>, <&de_fe_clk>, | |
377 | <&dram_gates 25>; | |
378 | clock-names = "ahb", "mod", | |
379 | "ram"; | |
380 | resets = <&de_fe_clk>; | |
381 | ||
382 | ports { | |
383 | #address-cells = <1>; | |
384 | #size-cells = <0>; | |
385 | ||
386 | fe0_out: port@1 { | |
387 | #address-cells = <1>; | |
388 | #size-cells = <0>; | |
389 | reg = <1>; | |
390 | ||
391 | fe0_out_be0: endpoint { | |
392 | remote-endpoint = <&be0_in_fe0>; | |
393 | }; | |
394 | }; | |
395 | }; | |
396 | }; | |
397 | ||
398 | be0: display-backend@1e60000 { | |
399 | compatible = "allwinner,sun5i-a13-display-backend"; | |
400 | reg = <0x01e60000 0x10000>; | |
9904e70a | 401 | interrupts = <47>; |
21a454fd MR |
402 | clocks = <&ahb_gates 44>, <&de_be_clk>, |
403 | <&dram_gates 26>; | |
404 | clock-names = "ahb", "mod", | |
405 | "ram"; | |
406 | resets = <&de_be_clk>; | |
407 | ||
408 | ports { | |
409 | #address-cells = <1>; | |
410 | #size-cells = <0>; | |
411 | ||
412 | be0_in: port@0 { | |
413 | #address-cells = <1>; | |
414 | #size-cells = <0>; | |
415 | reg = <0>; | |
416 | ||
417 | be0_in_fe0: endpoint@0 { | |
418 | reg = <0>; | |
419 | remote-endpoint = <&fe0_out_be0>; | |
420 | }; | |
421 | }; | |
422 | ||
423 | be0_out: port@1 { | |
424 | #address-cells = <1>; | |
425 | #size-cells = <0>; | |
426 | reg = <1>; | |
427 | ||
428 | be0_out_tcon0: endpoint@0 { | |
429 | reg = <0>; | |
430 | remote-endpoint = <&tcon0_in_be0>; | |
431 | }; | |
432 | }; | |
433 | }; | |
434 | }; | |
435 | ||
436 | display-engine { | |
437 | compatible = "allwinner,sun5i-a13-display-engine"; | |
438 | allwinner,pipelines = <&fe0>; | |
439 | }; |