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1I2C for Atmel platforms
2
3Required properties :
4- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
0ba82c95 5 "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
cc018e36 6 "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
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7- reg: physical base address of the controller and length of memory mapped
8 region.
9- interrupts: interrupt number to the cpu.
10- #address-cells = <1>;
11- #size-cells = <0>;
c21e5c76 12- clocks: phandles to input clocks.
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13
14Optional properties:
75b6c4b6 15- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
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16- dmas: A list of two dma specifiers, one for each entry in dma-names.
17- dma-names: should contain "tx" and "rx".
18- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
19 capable I2C controllers.
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20- i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c"
21 and "atmel,sama5d2-i2c".
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22- Child nodes conforming to i2c bus binding
23
24Examples :
25
26i2c0: i2c@fff84000 {
27 compatible = "atmel,at91sam9g20-i2c";
28 reg = <0xfff84000 0x100>;
29 interrupts = <12 4 6>;
30 #address-cells = <1>;
31 #size-cells = <0>;
c21e5c76 32 clocks = <&twi0_clk>;
75b6c4b6 33 clock-frequency = <400000>;
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34
35 24c512@50 {
36 compatible = "24c512";
37 reg = <0x50>;
38 pagesize = <128>;
39 }
40}
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41
42i2c0: i2c@f8034600 {
43 compatible = "atmel,sama5d2-i2c";
44 reg = <0xf8034600 0x100>;
45 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
46 dmas = <&dma0
47 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
48 AT91_XDMAC_DT_PERID(11)>,
49 <&dma0
50 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
51 AT91_XDMAC_DT_PERID(12)>;
52 dma-names = "tx", "rx";
53 #address-cells = <1>;
54 #size-cells = <0>;
55 clocks = <&flx0>;
56 atmel,fifo-size = <16>;
cc018e36 57 i2c-sda-hold-time-ns = <336>;
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58
59 wm8731: wm8731@1a {
60 compatible = "wm8731";
61 reg = <0x1a>;
62 };
63};