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Commit | Line | Data |
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dfcd04b1 SG |
1 | * Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX |
2 | ||
3 | Required properties: | |
e66ff0a9 JL |
4 | - compatible : |
5 | - "fsl,imx1-i2c" for I2C compatible with the one integrated on i.MX1 SoC | |
6 | - "fsl,imx21-i2c" for I2C compatible with the one integrated on i.MX21 SoC | |
7 | - "fsl,vf610-i2c" for I2C compatible with the one integrated on Vybrid vf610 SoC | |
dfcd04b1 SG |
8 | - reg : Should contain I2C/HS-I2C registers location and length |
9 | - interrupts : Should contain I2C/HS-I2C interrupt | |
5d232112 | 10 | - clocks : Should contain the I2C/HS-I2C clock specifier |
dfcd04b1 SG |
11 | |
12 | Optional properties: | |
13 | - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz. | |
14 | The absence of the propoerty indicates the default frequency 100 kHz. | |
ce1a7884 YY |
15 | - dmas: A list of two dma specifiers, one for each entry in dma-names. |
16 | - dma-names: should contain "tx" and "rx". | |
dfcd04b1 SG |
17 | |
18 | Examples: | |
19 | ||
20 | i2c@83fc4000 { /* I2C2 on i.MX51 */ | |
5bdfba29 | 21 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
dfcd04b1 SG |
22 | reg = <0x83fc4000 0x4000>; |
23 | interrupts = <63>; | |
24 | }; | |
25 | ||
26 | i2c@70038000 { /* HS-I2C on i.MX51 */ | |
5bdfba29 | 27 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
dfcd04b1 SG |
28 | reg = <0x70038000 0x4000>; |
29 | interrupts = <64>; | |
30 | clock-frequency = <400000>; | |
31 | }; | |
ce1a7884 YY |
32 | |
33 | i2c0: i2c@40066000 { /* i2c0 on vf610 */ | |
34 | compatible = "fsl,vf610-i2c"; | |
35 | reg = <0x40066000 0x1000>; | |
36 | interrupts =<0 71 0x04>; | |
37 | dmas = <&edma0 0 50>, | |
38 | <&edma0 0 51>; | |
39 | dma-names = "rx","tx"; | |
40 | }; |