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5698c50d JH |
1 | * Meta External Trigger Controller Binding |
2 | ||
3 | This binding specifies what properties must be available in the device tree | |
4 | representation of a Meta external trigger controller. | |
5 | ||
6 | Required properties: | |
7 | ||
8 | - compatible: Specifies the compatibility list for the interrupt controller. | |
9 | The type shall be <string> and the value shall include "img,meta-intc". | |
10 | ||
11 | - num-banks: Specifies the number of interrupt banks (each of which can | |
12 | handle 32 interrupt sources). | |
13 | ||
14 | - interrupt-controller: The presence of this property identifies the node | |
372c1d6d | 15 | as an interrupt controller. No property value shall be defined. |
5698c50d JH |
16 | |
17 | - #interrupt-cells: Specifies the number of cells needed to encode an | |
18 | interrupt source. The type shall be a <u32> and the value shall be 2. | |
19 | ||
20 | - #address-cells: Specifies the number of cells needed to encode an | |
21 | address. The type shall be <u32> and the value shall be 0. As such, | |
22 | 'interrupt-map' nodes do not have to specify a parent unit address. | |
23 | ||
24 | Optional properties: | |
25 | ||
26 | - no-mask: The controller doesn't have any mask registers. | |
27 | ||
28 | * Interrupt Specifier Definition | |
29 | ||
30 | Interrupt specifiers consists of 2 cells encoded as follows: | |
31 | ||
32 | - <1st-cell>: The interrupt-number that identifies the interrupt source. | |
33 | ||
34 | - <2nd-cell>: The Linux interrupt flags containing level-sense information, | |
35 | encoded as follows: | |
36 | 1 = edge triggered | |
37 | 4 = level-sensitive | |
38 | ||
39 | * Examples | |
40 | ||
41 | Example 1: | |
42 | ||
43 | /* | |
44 | * Meta external trigger block | |
45 | */ | |
46 | intc: intc { | |
47 | // This is an interrupt controller node. | |
48 | interrupt-controller; | |
49 | ||
50 | // No address cells so that 'interrupt-map' nodes which | |
51 | // reference this interrupt controller node do not need a parent | |
52 | // address specifier. | |
53 | #address-cells = <0>; | |
54 | ||
55 | // Two cells to encode interrupt sources. | |
56 | #interrupt-cells = <2>; | |
57 | ||
58 | // Number of interrupt banks | |
59 | num-banks = <2>; | |
60 | ||
61 | // No HWMASKEXT is available (specify on Chorus2 and Comet ES1) | |
62 | no-mask; | |
63 | ||
64 | // Compatible with Meta hardware trigger block. | |
65 | compatible = "img,meta-intc"; | |
66 | }; | |
67 | ||
68 | Example 2: | |
69 | ||
70 | /* | |
71 | * An interrupt generating device that is wired to a Meta external | |
72 | * trigger block. | |
73 | */ | |
4c9847b7 | 74 | uart1: uart@02004c00 { |
5698c50d JH |
75 | // Interrupt source '5' that is level-sensitive. |
76 | // Note that there are only two cells as specified in the | |
77 | // interrupt parent's '#interrupt-cells' property. | |
78 | interrupts = <5 4 /* level */>; | |
79 | ||
80 | // The interrupt controller that this device is wired to. | |
81 | interrupt-parent = <&intc>; | |
82 | }; |