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Commit | Line | Data |
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eaf0ecc3 VG |
1 | * ARC-HS Interrupt Distribution Unit |
2 | ||
3 | This optional 2nd level interrupt controller can be used in SMP configurations for | |
4 | dynamic IRQ routing, load balancing of common/external IRQs towards core intc. | |
5 | ||
6 | Properties: | |
7 | ||
8 | - compatible: "snps,archs-idu-intc" | |
9 | - interrupt-controller: This is an interrupt controller. | |
10 | - interrupt-parent: <reference to parent core intc> | |
11 | - #interrupt-cells: Must be <2>. | |
12 | - interrupts: <...> specifies the upstream core irqs | |
13 | ||
14 | First cell specifies the "common" IRQ from peripheral to IDU | |
15 | Second cell specifies the irq distribution mode to cores | |
16 | 0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 | |
17 | ||
92fdb527 YK |
18 | The second cell in interrupts property is deprecated and may be ignored by |
19 | the kernel. | |
20 | ||
eaf0ecc3 VG |
21 | intc accessed via the special ARC AUX register interface, hence "reg" property |
22 | is not specified. | |
23 | ||
24 | Example: | |
25 | core_intc: core-interrupt-controller { | |
26 | compatible = "snps,archs-intc"; | |
27 | interrupt-controller; | |
28 | #interrupt-cells = <1>; | |
29 | }; | |
30 | ||
31 | idu_intc: idu-interrupt-controller { | |
32 | compatible = "snps,archs-idu-intc"; | |
33 | interrupt-controller; | |
34 | interrupt-parent = <&core_intc>; | |
35 | ||
36 | /* | |
37 | * <hwirq distribution> | |
38 | * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 | |
39 | */ | |
40 | #interrupt-cells = <2>; | |
41 | ||
42 | /* upstream core irqs: downstream these are "COMMON" irq 0,1.. */ | |
43 | interrupts = <24 25 26 27 28 29 30 31>; | |
44 | }; | |
45 | ||
46 | some_device: serial@c0fc1000 { | |
47 | interrupt-parent = <&idu_intc>; | |
48 | interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */ | |
49 | }; |