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Commit | Line | Data |
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a8689f65 FV |
1 | OMAP2+ IOMMU |
2 | ||
3 | Required properties: | |
4 | - compatible : Should be one of, | |
5 | "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances | |
6 | "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances | |
7 | "ti,dra7-iommu" for DRA7xx IOMMU instances | |
8 | - ti,hwmods : Name of the hwmod associated with the IOMMU instance | |
9 | - reg : Address space for the configuration registers | |
10 | - interrupts : Interrupt specifier for the IOMMU instance | |
a73622a7 SA |
11 | - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices, |
12 | and needs no additional data in the pargs specifier. Please | |
13 | also refer to the generic bindings document for more info | |
14 | on this property, | |
15 | Documentation/devicetree/bindings/iommu/iommu.txt | |
a8689f65 FV |
16 | |
17 | Optional properties: | |
18 | - ti,#tlb-entries : Number of entries in the translation look-aside buffer. | |
19 | Should be either 8 or 32 (default: 32) | |
20 | - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing | |
21 | back a bus error response on MMU faults. | |
22 | ||
23 | Example: | |
24 | /* OMAP3 ISP MMU */ | |
25 | mmu_isp: mmu@480bd400 { | |
a73622a7 | 26 | #iommu-cells = <0>; |
a8689f65 FV |
27 | compatible = "ti,omap2-iommu"; |
28 | reg = <0x480bd400 0x80>; | |
29 | interrupts = <24>; | |
30 | ti,hwmods = "mmu_isp"; | |
31 | ti,#tlb-entries = <8>; | |
32 | }; |