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1 | Marvell Discovery mv64[345]6x System Controller chips |
2 | =========================================================== | |
3 | ||
4 | The Marvell mv64[345]60 series of system controller chips contain | |
5 | many of the peripherals needed to implement a complete computer | |
6 | system. In this section, we define device tree nodes to describe | |
7 | the system controller chip itself and each of the peripherals | |
8 | which it contains. Compatible string values for each node are | |
9 | prefixed with the string "marvell,", for Marvell Technology Group Ltd. | |
10 | ||
11 | 1) The /system-controller node | |
12 | ||
13 | This node is used to represent the system-controller and must be | |
14 | present when the system uses a system controller chip. The top-level | |
15 | system-controller node contains information that is global to all | |
16 | devices within the system controller chip. The node name begins | |
17 | with "system-controller" followed by the unit address, which is | |
18 | the base address of the memory-mapped register set for the system | |
19 | controller chip. | |
20 | ||
21 | Required properties: | |
22 | ||
23 | - ranges : Describes the translation of system controller addresses | |
24 | for memory mapped registers. | |
25 | - clock-frequency: Contains the main clock frequency for the system | |
26 | controller chip. | |
27 | - reg : This property defines the address and size of the | |
28 | memory-mapped registers contained within the system controller | |
29 | chip. The address specified in the "reg" property should match | |
30 | the unit address of the system-controller node. | |
31 | - #address-cells : Address representation for system controller | |
32 | devices. This field represents the number of cells needed to | |
33 | represent the address of the memory-mapped registers of devices | |
34 | within the system controller chip. | |
411c9403 | 35 | - #size-cells : Size representation for the memory-mapped |
b053dc5a KG |
36 | registers within the system controller chip. |
37 | - #interrupt-cells : Defines the width of cells used to represent | |
38 | interrupts. | |
39 | ||
40 | Optional properties: | |
41 | ||
42 | - model : The specific model of the system controller chip. Such | |
43 | as, "mv64360", "mv64460", or "mv64560". | |
44 | - compatible : A string identifying the compatibility identifiers | |
45 | of the system controller chip. | |
46 | ||
47 | The system-controller node contains child nodes for each system | |
48 | controller device that the platform uses. Nodes should not be created | |
49 | for devices which exist on the system controller chip but are not used | |
50 | ||
51 | Example Marvell Discovery mv64360 system-controller node: | |
52 | ||
53 | system-controller@f1000000 { /* Marvell Discovery mv64360 */ | |
54 | #address-cells = <1>; | |
55 | #size-cells = <1>; | |
56 | model = "mv64360"; /* Default */ | |
57 | compatible = "marvell,mv64360"; | |
58 | clock-frequency = <133333333>; | |
59 | reg = <0xf1000000 0x10000>; | |
60 | virtual-reg = <0xf1000000>; | |
61 | ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ | |
62 | 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ | |
63 | 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ | |
64 | 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ | |
65 | 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ | |
66 | ||
67 | [ child node definitions... ] | |
68 | } | |
69 | ||
70 | 2) Child nodes of /system-controller | |
71 | ||
72 | a) Marvell Discovery MDIO bus | |
73 | ||
74 | The MDIO is a bus to which the PHY devices are connected. For each | |
75 | device that exists on this bus, a child node should be created. See | |
76 | the definition of the PHY node below for an example of how to define | |
77 | a PHY. | |
78 | ||
79 | Required properties: | |
80 | - #address-cells : Should be <1> | |
81 | - #size-cells : Should be <0> | |
b053dc5a KG |
82 | - compatible : Should be "marvell,mv64360-mdio" |
83 | ||
84 | Example: | |
85 | ||
86 | mdio { | |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
b053dc5a KG |
89 | compatible = "marvell,mv64360-mdio"; |
90 | ||
91 | ethernet-phy@0 { | |
92 | ...... | |
93 | }; | |
94 | }; | |
95 | ||
96 | ||
97 | b) Marvell Discovery ethernet controller | |
98 | ||
99 | The Discover ethernet controller is described with two levels | |
100 | of nodes. The first level describes an ethernet silicon block | |
101 | and the second level describes up to 3 ethernet nodes within | |
102 | that block. The reason for the multiple levels is that the | |
103 | registers for the node are interleaved within a single set | |
104 | of registers. The "ethernet-block" level describes the | |
105 | shared register set, and the "ethernet" nodes describe ethernet | |
106 | port-specific properties. | |
107 | ||
108 | Ethernet block node | |
109 | ||
110 | Required properties: | |
111 | - #address-cells : <1> | |
112 | - #size-cells : <0> | |
113 | - compatible : "marvell,mv64360-eth-block" | |
114 | - reg : Offset and length of the register set for this block | |
115 | ||
20922486 SH |
116 | Optional properties: |
117 | - clocks : Phandle to the clock control device and gate bit | |
118 | ||
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119 | Example Discovery Ethernet block node: |
120 | ethernet-block@2000 { | |
121 | #address-cells = <1>; | |
122 | #size-cells = <0>; | |
123 | compatible = "marvell,mv64360-eth-block"; | |
124 | reg = <0x2000 0x2000>; | |
125 | ethernet@0 { | |
126 | ....... | |
127 | }; | |
128 | }; | |
129 | ||
130 | Ethernet port node | |
131 | ||
132 | Required properties: | |
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133 | - compatible : Should be "marvell,mv64360-eth". |
134 | - reg : Should be <0>, <1>, or <2>, according to which registers | |
135 | within the silicon block the device uses. | |
136 | - interrupts : <a> where a is the interrupt number for the port. | |
137 | - interrupt-parent : the phandle for the interrupt controller | |
138 | that services interrupts for this device. | |
139 | - phy : the phandle for the PHY connected to this ethernet | |
140 | controller. | |
141 | - local-mac-address : 6 bytes, MAC address | |
142 | ||
143 | Example Discovery Ethernet port node: | |
144 | ethernet@0 { | |
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145 | compatible = "marvell,mv64360-eth"; |
146 | reg = <0>; | |
147 | interrupts = <32>; | |
148 | interrupt-parent = <&PIC>; | |
149 | phy = <&PHY0>; | |
150 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
151 | }; | |
152 | ||
153 | ||
154 | ||
155 | c) Marvell Discovery PHY nodes | |
156 | ||
157 | Required properties: | |
b053dc5a KG |
158 | - interrupts : <a> where a is the interrupt number for this phy. |
159 | - interrupt-parent : the phandle for the interrupt controller that | |
160 | services interrupts for this device. | |
161 | - reg : The ID number for the phy, usually a small integer | |
162 | ||
163 | Example Discovery PHY node: | |
164 | ethernet-phy@1 { | |
b053dc5a KG |
165 | compatible = "broadcom,bcm5421"; |
166 | interrupts = <76>; /* GPP 12 */ | |
167 | interrupt-parent = <&PIC>; | |
168 | reg = <1>; | |
169 | }; | |
170 | ||
171 | ||
172 | d) Marvell Discovery SDMA nodes | |
173 | ||
174 | Represent DMA hardware associated with the MPSC (multiprotocol | |
175 | serial controllers). | |
176 | ||
177 | Required properties: | |
178 | - compatible : "marvell,mv64360-sdma" | |
179 | - reg : Offset and length of the register set for this device | |
180 | - interrupts : <a> where a is the interrupt number for the DMA | |
181 | device. | |
182 | - interrupt-parent : the phandle for the interrupt controller | |
183 | that services interrupts for this device. | |
184 | ||
185 | Example Discovery SDMA node: | |
186 | sdma@4000 { | |
187 | compatible = "marvell,mv64360-sdma"; | |
188 | reg = <0x4000 0xc18>; | |
189 | virtual-reg = <0xf1004000>; | |
190 | interrupts = <36>; | |
191 | interrupt-parent = <&PIC>; | |
192 | }; | |
193 | ||
194 | ||
195 | e) Marvell Discovery BRG nodes | |
196 | ||
197 | Represent baud rate generator hardware associated with the MPSC | |
198 | (multiprotocol serial controllers). | |
199 | ||
200 | Required properties: | |
201 | - compatible : "marvell,mv64360-brg" | |
202 | - reg : Offset and length of the register set for this device | |
203 | - clock-src : A value from 0 to 15 which selects the clock | |
204 | source for the baud rate generator. This value corresponds | |
205 | to the CLKS value in the BRGx configuration register. See | |
206 | the mv64x60 User's Manual. | |
207 | - clock-frequence : The frequency (in Hz) of the baud rate | |
208 | generator's input clock. | |
209 | - current-speed : The current speed setting (presumably by | |
210 | firmware) of the baud rate generator. | |
211 | ||
212 | Example Discovery BRG node: | |
213 | brg@b200 { | |
214 | compatible = "marvell,mv64360-brg"; | |
215 | reg = <0xb200 0x8>; | |
216 | clock-src = <8>; | |
217 | clock-frequency = <133333333>; | |
218 | current-speed = <9600>; | |
219 | }; | |
220 | ||
221 | ||
222 | f) Marvell Discovery CUNIT nodes | |
223 | ||
224 | Represent the Serial Communications Unit device hardware. | |
225 | ||
226 | Required properties: | |
227 | - reg : Offset and length of the register set for this device | |
228 | ||
229 | Example Discovery CUNIT node: | |
230 | cunit@f200 { | |
231 | reg = <0xf200 0x200>; | |
232 | }; | |
233 | ||
234 | ||
235 | g) Marvell Discovery MPSCROUTING nodes | |
236 | ||
237 | Represent the Discovery's MPSC routing hardware | |
238 | ||
239 | Required properties: | |
240 | - reg : Offset and length of the register set for this device | |
241 | ||
242 | Example Discovery CUNIT node: | |
243 | mpscrouting@b500 { | |
244 | reg = <0xb400 0xc>; | |
245 | }; | |
246 | ||
247 | ||
248 | h) Marvell Discovery MPSCINTR nodes | |
249 | ||
250 | Represent the Discovery's MPSC DMA interrupt hardware registers | |
251 | (SDMA cause and mask registers). | |
252 | ||
253 | Required properties: | |
254 | - reg : Offset and length of the register set for this device | |
255 | ||
256 | Example Discovery MPSCINTR node: | |
257 | mpsintr@b800 { | |
258 | reg = <0xb800 0x100>; | |
259 | }; | |
260 | ||
261 | ||
262 | i) Marvell Discovery MPSC nodes | |
263 | ||
264 | Represent the Discovery's MPSC (Multiprotocol Serial Controller) | |
265 | serial port. | |
266 | ||
267 | Required properties: | |
b053dc5a KG |
268 | - compatible : "marvell,mv64360-mpsc" |
269 | - reg : Offset and length of the register set for this device | |
270 | - sdma : the phandle for the SDMA node used by this port | |
271 | - brg : the phandle for the BRG node used by this port | |
272 | - cunit : the phandle for the CUNIT node used by this port | |
273 | - mpscrouting : the phandle for the MPSCROUTING node used by this port | |
274 | - mpscintr : the phandle for the MPSCINTR node used by this port | |
275 | - cell-index : the hardware index of this cell in the MPSC core | |
276 | - max_idle : value needed for MPSC CHR3 (Maximum Frame Length) | |
277 | register | |
278 | - interrupts : <a> where a is the interrupt number for the MPSC. | |
279 | - interrupt-parent : the phandle for the interrupt controller | |
280 | that services interrupts for this device. | |
281 | ||
282 | Example Discovery MPSCINTR node: | |
283 | mpsc@8000 { | |
b053dc5a KG |
284 | compatible = "marvell,mv64360-mpsc"; |
285 | reg = <0x8000 0x38>; | |
286 | virtual-reg = <0xf1008000>; | |
287 | sdma = <&SDMA0>; | |
288 | brg = <&BRG0>; | |
289 | cunit = <&CUNIT>; | |
290 | mpscrouting = <&MPSCROUTING>; | |
291 | mpscintr = <&MPSCINTR>; | |
292 | cell-index = <0>; | |
293 | max_idle = <40>; | |
294 | interrupts = <40>; | |
295 | interrupt-parent = <&PIC>; | |
296 | }; | |
297 | ||
298 | ||
299 | j) Marvell Discovery Watch Dog Timer nodes | |
300 | ||
301 | Represent the Discovery's watchdog timer hardware | |
302 | ||
303 | Required properties: | |
304 | - compatible : "marvell,mv64360-wdt" | |
305 | - reg : Offset and length of the register set for this device | |
306 | ||
307 | Example Discovery Watch Dog Timer node: | |
308 | wdt@b410 { | |
309 | compatible = "marvell,mv64360-wdt"; | |
310 | reg = <0xb410 0x8>; | |
311 | }; | |
312 | ||
313 | ||
314 | k) Marvell Discovery I2C nodes | |
315 | ||
316 | Represent the Discovery's I2C hardware | |
317 | ||
318 | Required properties: | |
319 | - device_type : "i2c" | |
320 | - compatible : "marvell,mv64360-i2c" | |
321 | - reg : Offset and length of the register set for this device | |
322 | - interrupts : <a> where a is the interrupt number for the I2C. | |
323 | - interrupt-parent : the phandle for the interrupt controller | |
324 | that services interrupts for this device. | |
325 | ||
326 | Example Discovery I2C node: | |
327 | compatible = "marvell,mv64360-i2c"; | |
328 | reg = <0xc000 0x20>; | |
329 | virtual-reg = <0xf100c000>; | |
330 | interrupts = <37>; | |
331 | interrupt-parent = <&PIC>; | |
332 | }; | |
333 | ||
334 | ||
335 | l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes | |
336 | ||
337 | Represent the Discovery's PIC hardware | |
338 | ||
339 | Required properties: | |
340 | - #interrupt-cells : <1> | |
341 | - #address-cells : <0> | |
342 | - compatible : "marvell,mv64360-pic" | |
343 | - reg : Offset and length of the register set for this device | |
344 | - interrupt-controller | |
345 | ||
346 | Example Discovery PIC node: | |
347 | pic { | |
348 | #interrupt-cells = <1>; | |
349 | #address-cells = <0>; | |
350 | compatible = "marvell,mv64360-pic"; | |
351 | reg = <0x0 0x88>; | |
352 | interrupt-controller; | |
353 | }; | |
354 | ||
355 | ||
356 | m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes | |
357 | ||
358 | Represent the Discovery's MPP hardware | |
359 | ||
360 | Required properties: | |
361 | - compatible : "marvell,mv64360-mpp" | |
362 | - reg : Offset and length of the register set for this device | |
363 | ||
364 | Example Discovery MPP node: | |
365 | mpp@f000 { | |
366 | compatible = "marvell,mv64360-mpp"; | |
367 | reg = <0xf000 0x10>; | |
368 | }; | |
369 | ||
370 | ||
371 | n) Marvell Discovery GPP (General Purpose Pins) nodes | |
372 | ||
373 | Represent the Discovery's GPP hardware | |
374 | ||
375 | Required properties: | |
376 | - compatible : "marvell,mv64360-gpp" | |
377 | - reg : Offset and length of the register set for this device | |
378 | ||
379 | Example Discovery GPP node: | |
380 | gpp@f000 { | |
381 | compatible = "marvell,mv64360-gpp"; | |
382 | reg = <0xf100 0x20>; | |
383 | }; | |
384 | ||
385 | ||
386 | o) Marvell Discovery PCI host bridge node | |
387 | ||
388 | Represents the Discovery's PCI host bridge device. The properties | |
389 | for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE | |
390 | 1275-1994. A typical value for the compatible property is | |
391 | "marvell,mv64360-pci". | |
392 | ||
393 | Example Discovery PCI host bridge node | |
394 | pci@80000000 { | |
395 | #address-cells = <3>; | |
396 | #size-cells = <2>; | |
397 | #interrupt-cells = <1>; | |
398 | device_type = "pci"; | |
399 | compatible = "marvell,mv64360-pci"; | |
400 | reg = <0xcf8 0x8>; | |
401 | ranges = <0x01000000 0x0 0x0 | |
402 | 0x88000000 0x0 0x01000000 | |
403 | 0x02000000 0x0 0x80000000 | |
404 | 0x80000000 0x0 0x08000000>; | |
405 | bus-range = <0 255>; | |
406 | clock-frequency = <66000000>; | |
407 | interrupt-parent = <&PIC>; | |
408 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
409 | interrupt-map = < | |
410 | /* IDSEL 0x0a */ | |
411 | 0x5000 0 0 1 &PIC 80 | |
412 | 0x5000 0 0 2 &PIC 81 | |
413 | 0x5000 0 0 3 &PIC 91 | |
414 | 0x5000 0 0 4 &PIC 93 | |
415 | ||
416 | /* IDSEL 0x0b */ | |
417 | 0x5800 0 0 1 &PIC 91 | |
418 | 0x5800 0 0 2 &PIC 93 | |
419 | 0x5800 0 0 3 &PIC 80 | |
420 | 0x5800 0 0 4 &PIC 81 | |
421 | ||
422 | /* IDSEL 0x0c */ | |
423 | 0x6000 0 0 1 &PIC 91 | |
424 | 0x6000 0 0 2 &PIC 93 | |
425 | 0x6000 0 0 3 &PIC 80 | |
426 | 0x6000 0 0 4 &PIC 81 | |
427 | ||
428 | /* IDSEL 0x0d */ | |
429 | 0x6800 0 0 1 &PIC 93 | |
430 | 0x6800 0 0 2 &PIC 80 | |
431 | 0x6800 0 0 3 &PIC 81 | |
432 | 0x6800 0 0 4 &PIC 91 | |
433 | >; | |
434 | }; | |
435 | ||
436 | ||
437 | p) Marvell Discovery CPU Error nodes | |
438 | ||
439 | Represent the Discovery's CPU error handler device. | |
440 | ||
441 | Required properties: | |
442 | - compatible : "marvell,mv64360-cpu-error" | |
443 | - reg : Offset and length of the register set for this device | |
444 | - interrupts : the interrupt number for this device | |
445 | - interrupt-parent : the phandle for the interrupt controller | |
446 | that services interrupts for this device. | |
447 | ||
448 | Example Discovery CPU Error node: | |
449 | cpu-error@0070 { | |
450 | compatible = "marvell,mv64360-cpu-error"; | |
451 | reg = <0x70 0x10 0x128 0x28>; | |
452 | interrupts = <3>; | |
453 | interrupt-parent = <&PIC>; | |
454 | }; | |
455 | ||
456 | ||
457 | q) Marvell Discovery SRAM Controller nodes | |
458 | ||
459 | Represent the Discovery's SRAM controller device. | |
460 | ||
461 | Required properties: | |
462 | - compatible : "marvell,mv64360-sram-ctrl" | |
463 | - reg : Offset and length of the register set for this device | |
464 | - interrupts : the interrupt number for this device | |
465 | - interrupt-parent : the phandle for the interrupt controller | |
466 | that services interrupts for this device. | |
467 | ||
468 | Example Discovery SRAM Controller node: | |
469 | sram-ctrl@0380 { | |
470 | compatible = "marvell,mv64360-sram-ctrl"; | |
471 | reg = <0x380 0x80>; | |
472 | interrupts = <13>; | |
473 | interrupt-parent = <&PIC>; | |
474 | }; | |
475 | ||
476 | ||
477 | r) Marvell Discovery PCI Error Handler nodes | |
478 | ||
479 | Represent the Discovery's PCI error handler device. | |
480 | ||
481 | Required properties: | |
482 | - compatible : "marvell,mv64360-pci-error" | |
483 | - reg : Offset and length of the register set for this device | |
484 | - interrupts : the interrupt number for this device | |
485 | - interrupt-parent : the phandle for the interrupt controller | |
486 | that services interrupts for this device. | |
487 | ||
488 | Example Discovery PCI Error Handler node: | |
489 | pci-error@1d40 { | |
490 | compatible = "marvell,mv64360-pci-error"; | |
491 | reg = <0x1d40 0x40 0xc28 0x4>; | |
492 | interrupts = <12>; | |
493 | interrupt-parent = <&PIC>; | |
494 | }; | |
495 | ||
496 | ||
497 | s) Marvell Discovery Memory Controller nodes | |
498 | ||
499 | Represent the Discovery's memory controller device. | |
500 | ||
501 | Required properties: | |
502 | - compatible : "marvell,mv64360-mem-ctrl" | |
503 | - reg : Offset and length of the register set for this device | |
504 | - interrupts : the interrupt number for this device | |
505 | - interrupt-parent : the phandle for the interrupt controller | |
506 | that services interrupts for this device. | |
507 | ||
508 | Example Discovery Memory Controller node: | |
509 | mem-ctrl@1400 { | |
510 | compatible = "marvell,mv64360-mem-ctrl"; | |
511 | reg = <0x1400 0x60>; | |
512 | interrupts = <17>; | |
513 | interrupt-parent = <&PIC>; | |
514 | }; | |
515 | ||
516 |