projects / mirror_ubuntu-jammy-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 56fb34d8 BG |
1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 | |
| 3 | --- | |
| 4 | $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml# | |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | ||
| 7 | title: STMicroelectronics STM32 Timers bindings | |
| 8 | ||
| 9 | description: | | |
| 10 | This hardware block provides 3 types of timer along with PWM functionality: | |
| 11 | - advanced-control timers consist of a 16-bit auto-reload counter driven | |
| 12 | by a programmable prescaler, break input feature, PWM outputs and | |
| 13 | complementary PWM outputs channels. | |
| 14 | - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter | |
| 15 | driven by a programmable prescaler and PWM outputs. | |
| 16 | - basic timers consist of a 16-bit auto-reload counter driven by a | |
| 17 | programmable prescaler. | |
| 18 | ||
| 19 | maintainers: | |
| 20 | - Benjamin Gaignard <benjamin.gaignard@st.com> | |
| 21 | - Fabrice Gasnier <fabrice.gasnier@st.com> | |
| 22 | ||
| 23 | properties: | |
| 24 | compatible: | |
| 25 | const: st,stm32-timers | |
| 26 | ||
| 27 | reg: | |
| 28 | maxItems: 1 | |
| 29 | ||
| 30 | clocks: | |
| 31 | maxItems: 1 | |
| 32 | ||
| 33 | clock-names: | |
| 34 | items: | |
| 35 | - const: int | |
| 36 | ||
| 37 | reset: | |
| 38 | maxItems: 1 | |
| 39 | ||
| 40 | dmas: | |
| 41 | minItems: 1 | |
| 42 | maxItems: 7 | |
| 43 | ||
| 44 | dma-names: | |
| 45 | items: | |
| 46 | enum: [ ch1, ch2, ch3, ch4, up, trig, com ] | |
| 47 | minItems: 1 | |
| 48 | maxItems: 7 | |
| 49 | ||
| 50 | "#address-cells": | |
| 51 | const: 1 | |
| 52 | ||
| 53 | "#size-cells": | |
| 54 | const: 0 | |
| 55 | ||
| 56 | pwm: | |
| 57 | type: object | |
| 58 | ||
| 59 | properties: | |
| 60 | compatible: | |
| 61 | const: st,stm32-pwm | |
| 62 | ||
| 63 | "#pwm-cells": | |
| 64 | const: 3 | |
| 65 | ||
| 66 | st,breakinput: | |
| 67 | description: | |
| 68 | One or two <index level filter> to describe break input | |
| 69 | configurations. | |
| 3d21a460 RH |
70 | $ref: /schemas/types.yaml#/definitions/uint32-matrix |
| 71 | items: | |
| 72 | items: | |
| 73 | - description: | | |
| 74 | "index" indicates on which break input (0 or 1) the | |
| 75 | configuration should be applied. | |
| 76 | enum: [0, 1] | |
| 77 | - description: | | |
| 78 | "level" gives the active level (0=low or 1=high) of the | |
| 79 | input signal for this configuration | |
| 80 | enum: [0, 1] | |
| 81 | - description: | | |
| 82 | "filter" gives the filtering value (up to 15) to be applied. | |
| 83 | maximum: 15 | |
| 84 | minItems: 1 | |
| 85 | maxItems: 2 | |
| 56fb34d8 BG |
86 | |
| 87 | required: | |
| 88 | - "#pwm-cells" | |
| 89 | - compatible | |
| 90 | ||
| 91 | patternProperties: | |
| 92 | "^timer@[0-9]+$": | |
| 93 | type: object | |
| 94 | ||
| 95 | properties: | |
| 96 | compatible: | |
| 97 | enum: | |
| 98 | - st,stm32-timer-trigger | |
| 99 | - st,stm32h7-timer-trigger | |
| 100 | ||
| 101 | reg: | |
| 102 | description: Identify trigger hardware block. | |
| 103 | items: | |
| 9f60a65b RH |
104 | minimum: 0 |
| 105 | maximum: 16 | |
| 56fb34d8 BG |
106 | |
| 107 | required: | |
| 108 | - compatible | |
| 109 | - reg | |
| 110 | ||
| 111 | counter: | |
| 112 | type: object | |
| 113 | ||
| 114 | properties: | |
| 115 | compatible: | |
| 116 | const: st,stm32-timer-counter | |
| 117 | ||
| 118 | required: | |
| 119 | - compatible | |
| 120 | ||
| 121 | required: | |
| 122 | - "#address-cells" | |
| 123 | - "#size-cells" | |
| 124 | - compatible | |
| 125 | - reg | |
| 126 | - clocks | |
| 127 | - clock-names | |
| 128 | ||
| 129 | additionalProperties: false | |
| 130 | ||
| 131 | examples: | |
| 132 | - | | |
| 133 | #include <dt-bindings/clock/stm32mp1-clks.h> | |
| 8f7e68bb | 134 | timers2: timer@40000000 { |
| 56fb34d8 BG |
135 | #address-cells = <1>; |
| 136 | #size-cells = <0>; | |
| 137 | compatible = "st,stm32-timers"; | |
| 138 | reg = <0x40000000 0x400>; | |
| 139 | clocks = <&rcc TIM2_K>; | |
| 140 | clock-names = "int"; | |
| 141 | dmas = <&dmamux1 18 0x400 0x1>, | |
| 142 | <&dmamux1 19 0x400 0x1>, | |
| 143 | <&dmamux1 20 0x400 0x1>, | |
| 144 | <&dmamux1 21 0x400 0x1>, | |
| 145 | <&dmamux1 22 0x400 0x1>; | |
| 146 | dma-names = "ch1", "ch2", "ch3", "ch4", "up"; | |
| 147 | pwm { | |
| 148 | compatible = "st,stm32-pwm"; | |
| 149 | #pwm-cells = <3>; | |
| 150 | st,breakinput = <0 1 5>; | |
| 151 | }; | |
| 8f7e68bb | 152 | timer@1 { |
| 56fb34d8 | 153 | compatible = "st,stm32-timer-trigger"; |
| 8f7e68bb | 154 | reg = <1>; |
| 56fb34d8 BG |
155 | }; |
| 156 | counter { | |
| 157 | compatible = "st,stm32-timer-counter"; | |
| 158 | }; | |
| 159 | }; | |
| 160 | ||
| 161 | ... |