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Commit | Line | Data |
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913097bc BH |
1 | * ASPEED AST2400 and AST2500 coprocessor interrupt controller |
2 | ||
3 | This file describes the bindings for the interrupt controller present | |
4 | in the AST2400 and AST2500 BMC SoCs which provides interrupt to the | |
5 | ColdFire coprocessor. | |
6 | ||
7 | It is not a normal interrupt controller and it would be rather | |
8 | inconvenient to create an interrupt tree for it as it somewhat shares | |
9 | some of the same sources as the main ARM interrupt controller but with | |
10 | different numbers. | |
11 | ||
12 | The AST2500 supports a SW generated interrupt | |
13 | ||
14 | Required properties: | |
15 | - reg: address and length of the register for the device. | |
16 | - compatible: "aspeed,cvic" and one of: | |
17 | "aspeed,ast2400-cvic" | |
18 | or | |
19 | "aspeed,ast2500-cvic" | |
20 | ||
21 | - valid-sources: One cell, bitmap of supported sources for the implementation | |
22 | ||
23 | Optional properties; | |
24 | - copro-sw-interrupts: List of interrupt numbers that can be used as | |
25 | SW interrupts from the ARM to the coprocessor. | |
26 | (AST2500 only) | |
27 | ||
28 | Example: | |
29 | ||
30 | cvic: copro-interrupt-controller@1e6c2000 { | |
31 | compatible = "aspeed,ast2500-cvic"; | |
32 | valid-sources = <0xffffffff>; | |
33 | copro-sw-interrupts = <1>; | |
34 | reg = <0x1e6c2000 0x80>; | |
35 | }; |