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1Amlogic SD / eMMC controller for S905/GXBB family SoCs
2
3The MMC 5.1 compliant host controller on Amlogic provides the
4interface for SD, eMMC and SDIO devices.
5
6This file documents the properties in addition to those available in
7the MMC core bindings, documented by mmc.txt.
8
9Required properties:
10- compatible : contains one of:
11 - "amlogic,meson-gx-mmc"
12 - "amlogic,meson-gxbb-mmc"
13 - "amlogic,meson-gxl-mmc"
14 - "amlogic,meson-gxm-mmc"
15- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
16- clock-names: Should contain the following:
17 "core" - Main peripheral bus clock
18 "clkin0" - Parent clock of internal mux
19 "clkin1" - Other parent clock of internal mux
bdf63108 20 The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
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21 clock rate requested by the MMC core.
22
23Example:
24
25 sd_emmc_a: mmc@70000 {
26 compatible = "amlogic,meson-gxbb-mmc";
27 reg = <0x0 0x70000 0x0 0x2000>;
28 interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
29 clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
30 clock-names = "core", "clkin0", "clkin1";
31 pinctrl-0 = <&emmc_pins>;
32 };