[mirror_ubuntu-artful-kernel.git] / Documentation / devicetree / bindings / mmc / exynos-dw-mshc.txt

* Samsung Exynos specific extensions to the Synopsys Designware Mobile
  Storage Host Controller

The Synopsys designware mobile storage host controller is used to interface
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
differences between the core Synopsys dw mshc controller properties described
by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
extensions to the Synopsys Designware Mobile Storage Host Controller.

Required Properties:

* compatible: should be
	- "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
	  specific extensions.
	- "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
	  specific extensions.
	- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
	  specific extensions.
	- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
	  specific extensions.
	- "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
	  specific extensions.
	- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
	  specific extensions having an SMU.

* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
  unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
  ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.

* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
  in transmit mode and CIU clock phase shift value in receive mode for single
  data rate mode operation. Refer notes below for the order of the cells and the
  valid values.

* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
  in transmit mode and CIU clock phase shift value in receive mode for double
  data rate mode operation. Refer notes below for the order of the cells and the
  valid values.
* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
  shift value for hs400 mode operation.

  Notes for the sdr-timing and ddr-timing values:

    The order of the cells should be
      - First Cell: CIU clock phase shift value for tx mode.
      - Second Cell: CIU clock phase shift value for rx mode.

    Valid values for SDR and DDR CIU clock timing for Exynos5250:
      - valid value for tx phase shift and rx phase shift is 0 to 7.
      - when CIU clock divider value is set to 3, all possible 8 phase shift
        values can be used.
      - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
        phase shift clocks should be 0.

* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
  (Latency value for delay line in Read path)

Required properties for a slot (Deprecated - Recommend to use one slot per host):

* gpios: specifies a list of gpios used for command, clock and data bus. The
  first gpio is the command line and the second gpio is the clock line. The
  rest of the gpios (depending on the bus-width property) are the data lines in
  no particular order. The format of the gpio specifier depends on the gpio
  controller.
(Deprecated - Refer to Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)

Example:

  The MSHC controller node can be split into two portions, SoC specific and
  board specific portions as listed below.

	dwmmc0@12200000 {
		compatible = "samsung,exynos5250-dw-mshc";
		reg = <0x12200000 0x1000>;
		interrupts = <0 75 0>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	dwmmc0@12200000 {
		cap-mmc-highspeed;
		cap-sd-highspeed;
		broken-cd;
		fifo-depth = <0x80>;
		card-detect-delay = <200>;
		samsung,dw-mshc-ciu-div = <3>;
		samsung,dw-mshc-sdr-timing = <2 3>;
		samsung,dw-mshc-ddr-timing = <1 2>;
		samsung,dw-mshc-hs400-timing = <0 2>;
		samsung,read-strobe-delay = <90>;
		bus-width = <8>;
	};
Commit	Line	Data
53126a2f	1	* Samsung Exynos specific extensions to the Synopsys Designware Mobile
c3665006 TA	2	Storage Host Controller
c3665006 TA	3
53126a2f	4	The Synopsys designware mobile storage host controller is used to interface
c3665006	5	a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
53126a2f DN	6	differences between the core Synopsys dw mshc controller properties described
	7	by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
	8	extensions to the Synopsys Designware Mobile Storage Host Controller.
c3665006 TA	9
	10	Required Properties:
	11
	12	* compatible: should be
	13	- "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
f21ccfa0	14	specific extensions.
c3665006	15	- "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
f21ccfa0	16	specific extensions.
c3665006	17	- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
f21ccfa0	18	specific extensions.
0e2c5915 YK	19	- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
0e2c5915 YK	20	specific extensions.
89ad2be7 AK	21	- "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
	22	specific extensions.
	23	- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
	24	specific extensions having an SMU.
c3665006 TA	25
	26	* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
	27	unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
	28	ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
	29
	30	* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
	31	in transmit mode and CIU clock phase shift value in receive mode for single
	32	data rate mode operation. Refer notes below for the order of the cells and the
	33	valid values.
	34
	35	* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
	36	in transmit mode and CIU clock phase shift value in receive mode for double
	37	data rate mode operation. Refer notes below for the order of the cells and the
	38	valid values.
80113132 SJ	39	* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
80113132 SJ	40	shift value for hs400 mode operation.
c3665006 TA	41
	42	Notes for the sdr-timing and ddr-timing values:
	43
	44	The order of the cells should be
	45	- First Cell: CIU clock phase shift value for tx mode.
	46	- Second Cell: CIU clock phase shift value for rx mode.
	47
	48	Valid values for SDR and DDR CIU clock timing for Exynos5250:
	49	- valid value for tx phase shift and rx phase shift is 0 to 7.
	50	- when CIU clock divider value is set to 3, all possible 8 phase shift
	51	values can be used.
	52	- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
	53	phase shift clocks should be 0.
	54
80113132 SJ	55	* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
	56	(Latency value for delay line in Read path)
	57
c83c8737	58	Required properties for a slot (Deprecated - Recommend to use one slot per host):
c3665006 TA	59
	60	* gpios: specifies a list of gpios used for command, clock and data bus. The
	61	first gpio is the command line and the second gpio is the clock line. The
	62	rest of the gpios (depending on the bus-width property) are the data lines in
	63	no particular order. The format of the gpio specifier depends on the gpio
	64	controller.
c83c8737	65	(Deprecated - Refer to Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)
c3665006 TA	66
	67	Example:
	68
	69	The MSHC controller node can be split into two portions, SoC specific and
	70	board specific portions as listed below.
	71
	72	dwmmc0@12200000 {
	73	compatible = "samsung,exynos5250-dw-mshc";
	74	reg = <0x12200000 0x1000>;
	75	interrupts = <0 75 0>;
	76	#address-cells = <1>;
	77	#size-cells = <0>;
	78	};
	79
	80	dwmmc0@12200000 {
c83c8737 JC	81	cap-mmc-highspeed;
c83c8737 JC	82	cap-sd-highspeed;
c3665006 TA	83	broken-cd;
	84	fifo-depth = <0x80>;
	85	card-detect-delay = <200>;
	86	samsung,dw-mshc-ciu-div = <3>;
	87	samsung,dw-mshc-sdr-timing = <2 3>;
	88	samsung,dw-mshc-ddr-timing = <1 2>;
80113132 SJ	89	samsung,dw-mshc-hs400-timing = <0 2>;
80113132 SJ	90	samsung,read-strobe-delay = <90>;
c83c8737	91	bus-width = <8>;
c3665006	92	};