[mirror_ubuntu-zesty-kernel.git] / Documentation / devicetree / bindings / mmc / fsl-imx-esdhc.txt

* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX

The Enhanced Secure Digital Host Controller on Freescale i.MX family
provides an interface for MMC, SD, and SDIO types of memory cards.

This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.

Required properties:
- compatible : Should be "fsl,<chip>-esdhc"

Optional properties:
- fsl,cd-controller : Indicate to use controller internal card detection
- fsl,wp-controller : Indicate to use controller internal write protection
- fsl,delay-line : Specify the number of delay cells for override mode.
  This is used to set the clock delay for DLL(Delay Line) on override mode
  to select a proper data sampling window in case the clock quality is not good
  due to signal path is too long on the board. Please refer to eSDHC/uSDHC
  chapter, DLL (Delay Line) section in RM for details.
- voltage-ranges : Specify the voltage range in case there are software
  transparent level shifters on the outputs of the controller. Two cells are
  required, first cell specifies minimum slot voltage (mV), second cell
  specifies maximum slot voltage (mV). Several ranges could be specified.

Examples:

esdhc@70004000 {
	compatible = "fsl,imx51-esdhc";
	reg = <0x70004000 0x4000>;
	interrupts = <1>;
	fsl,cd-controller;
	fsl,wp-controller;
};

esdhc@70008000 {
	compatible = "fsl,imx51-esdhc";
	reg = <0x70008000 0x4000>;
	interrupts = <2>;
	cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
	wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
};
Commit	Line	Data
abfafc2d SG	1	* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
	2
	3	The Enhanced Secure Digital Host Controller on Freescale i.MX family
	4	provides an interface for MMC, SD, and SDIO types of memory cards.
	5
4efafee0 CB	6	This file documents differences between the core properties described
	7	by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
	8
abfafc2d SG	9	Required properties:
abfafc2d SG	10	- compatible : Should be "fsl,<chip>-esdhc"
abfafc2d SG	11
abfafc2d SG	12	Optional properties:
a46d2619 SG	13	- fsl,cd-controller : Indicate to use controller internal card detection
a46d2619 SG	14	- fsl,wp-controller : Indicate to use controller internal write protection
602519b2 DA	15	- fsl,delay-line : Specify the number of delay cells for override mode.
	16	This is used to set the clock delay for DLL(Delay Line) on override mode
	17	to select a proper data sampling window in case the clock quality is not good
	18	due to signal path is too long on the board. Please refer to eSDHC/uSDHC
	19	chapter, DLL (Delay Line) section in RM for details.
07bf2b54 SH	20	- voltage-ranges : Specify the voltage range in case there are software
	21	transparent level shifters on the outputs of the controller. Two cells are
	22	required, first cell specifies minimum slot voltage (mV), second cell
	23	specifies maximum slot voltage (mV). Several ranges could be specified.
abfafc2d SG	24
	25	Examples:
	26
	27	esdhc@70004000 {
	28	compatible = "fsl,imx51-esdhc";
	29	reg = <0x70004000 0x4000>;
	30	interrupts = <1>;
a46d2619 SG	31	fsl,cd-controller;
a46d2619 SG	32	fsl,wp-controller;
abfafc2d SG	33	};
	34
	35	esdhc@70008000 {
	36	compatible = "fsl,imx51-esdhc";
	37	reg = <0x70008000 0x4000>;
	38	interrupts = <2>;
06693fcd FE	39	cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
06693fcd FE	40	wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
abfafc2d	41	};