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1 | MTK SoCs NAND FLASH controller (NFC) DT binding |
2 | ||
3 | This file documents the device tree bindings for MTK SoCs NAND controllers. | |
4 | The functional split of the controller requires two drivers to operate: | |
5 | the nand controller interface driver and the ECC engine driver. | |
6 | ||
7 | The hardware description for both devices must be captured as device | |
8 | tree nodes. | |
9 | ||
10 | 1) NFC NAND Controller Interface (NFI): | |
11 | ======================================= | |
12 | ||
13 | The first part of NFC is NAND Controller Interface (NFI) HW. | |
14 | Required NFI properties: | |
2968698b XL |
15 | - compatible: Should be one of "mediatek,mt2701-nfc", |
16 | "mediatek,mt2712-nfc". | |
cac4fcc0 JRO |
17 | - reg: Base physical address and size of NFI. |
18 | - interrupts: Interrupts of NFI. | |
19 | - clocks: NFI required clocks. | |
20 | - clock-names: NFI clocks internal name. | |
21 | - status: Disabled default. Then set "okay" by platform. | |
22 | - ecc-engine: Required ECC Engine node. | |
23 | - #address-cells: NAND chip index, should be 1. | |
24 | - #size-cells: Should be 0. | |
25 | ||
26 | Example: | |
27 | ||
28 | nandc: nfi@1100d000 { | |
29 | compatible = "mediatek,mt2701-nfc"; | |
30 | reg = <0 0x1100d000 0 0x1000>; | |
31 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; | |
32 | clocks = <&pericfg CLK_PERI_NFI>, | |
33 | <&pericfg CLK_PERI_NFI_PAD>; | |
34 | clock-names = "nfi_clk", "pad_clk"; | |
35 | status = "disabled"; | |
36 | ecc-engine = <&bch>; | |
37 | #address-cells = <1>; | |
38 | #size-cells = <0>; | |
39 | }; | |
40 | ||
41 | Platform related properties, should be set in {platform_name}.dts: | |
42 | - children nodes: NAND chips. | |
43 | ||
44 | Children nodes properties: | |
45 | - reg: Chip Select Signal, default 0. | |
46 | Set as reg = <0>, <1> when need 2 CS. | |
47 | Optional: | |
48 | - nand-on-flash-bbt: Store BBT on NAND Flash. | |
49 | - nand-ecc-mode: the NAND ecc mode (check driver for supported modes) | |
50 | - nand-ecc-step-size: Number of data bytes covered by a single ECC step. | |
51 | valid values: 512 and 1024. | |
52 | 1024 is recommended for large page NANDs. | |
53 | - nand-ecc-strength: Number of bits to correct per ECC step. | |
54 | The valid values that the controller supports are: 4, 6, | |
55 | 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44, | |
56 | 48, 52, 56, 60. | |
57 | The strength should be calculated as follows: | |
58 | E = (S - F) * 8 / 14 | |
59 | S = O / (P / Q) | |
60 | E : nand-ecc-strength. | |
61 | S : spare size per sector. | |
62 | F : FDM size, should be in the range [1,8]. | |
63 | It is used to store free oob data. | |
64 | O : oob size. | |
65 | P : page size. | |
66 | Q : nand-ecc-step-size. | |
67 | If the result does not match any one of the listed | |
68 | choices above, please select the smaller valid value from | |
69 | the list. | |
70 | (otherwise the driver will do the adjustment at runtime) | |
71 | - pinctrl-names: Default NAND pin GPIO setting name. | |
72 | - pinctrl-0: GPIO setting node. | |
73 | ||
74 | Example: | |
75 | &pio { | |
76 | nand_pins_default: nanddefault { | |
77 | pins_dat { | |
78 | pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>, | |
79 | <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>, | |
80 | <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>, | |
81 | <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>, | |
82 | <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>, | |
83 | <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>, | |
84 | <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>, | |
85 | <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>, | |
86 | <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>; | |
87 | input-enable; | |
88 | drive-strength = <MTK_DRIVE_8mA>; | |
89 | bias-pull-up; | |
90 | }; | |
91 | ||
92 | pins_we { | |
93 | pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>; | |
94 | drive-strength = <MTK_DRIVE_8mA>; | |
95 | bias-pull-up = <MTK_PUPD_SET_R1R0_10>; | |
96 | }; | |
97 | ||
98 | pins_ale { | |
99 | pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>; | |
100 | drive-strength = <MTK_DRIVE_8mA>; | |
101 | bias-pull-down = <MTK_PUPD_SET_R1R0_10>; | |
102 | }; | |
103 | }; | |
104 | }; | |
105 | ||
106 | &nandc { | |
107 | status = "okay"; | |
108 | pinctrl-names = "default"; | |
109 | pinctrl-0 = <&nand_pins_default>; | |
110 | nand@0 { | |
111 | reg = <0>; | |
112 | nand-on-flash-bbt; | |
113 | nand-ecc-mode = "hw"; | |
114 | nand-ecc-strength = <24>; | |
115 | nand-ecc-step-size = <1024>; | |
116 | }; | |
117 | }; | |
118 | ||
119 | NAND chip optional subnodes: | |
120 | - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt | |
121 | ||
122 | Example: | |
123 | nand@0 { | |
124 | partitions { | |
125 | compatible = "fixed-partitions"; | |
126 | #address-cells = <1>; | |
127 | #size-cells = <1>; | |
128 | ||
129 | preloader@0 { | |
130 | label = "pl"; | |
131 | read-only; | |
132 | reg = <0x00000000 0x00400000>; | |
133 | }; | |
4c9847b7 | 134 | android@00400000 { |
cac4fcc0 JRO |
135 | label = "android"; |
136 | reg = <0x00400000 0x12c00000>; | |
137 | }; | |
138 | }; | |
139 | }; | |
140 | ||
141 | 2) ECC Engine: | |
142 | ============== | |
143 | ||
144 | Required BCH properties: | |
2968698b | 145 | - compatible: Should be one of "mediatek,mt2701-ecc", "mediatek,mt2712-ecc". |
cac4fcc0 JRO |
146 | - reg: Base physical address and size of ECC. |
147 | - interrupts: Interrupts of ECC. | |
148 | - clocks: ECC required clocks. | |
149 | - clock-names: ECC clocks internal name. | |
150 | - status: Disabled default. Then set "okay" by platform. | |
151 | ||
152 | Example: | |
153 | ||
154 | bch: ecc@1100e000 { | |
155 | compatible = "mediatek,mt2701-ecc"; | |
156 | reg = <0 0x1100e000 0 0x1000>; | |
157 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; | |
158 | clocks = <&pericfg CLK_PERI_NFI_ECC>; | |
159 | clock-names = "nfiecc_clk"; | |
160 | status = "disabled"; | |
161 | }; |