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1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/adi,adin.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Analog Devices ADIN1200/ADIN1300 PHY
8
9maintainers:
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
11
12description: |
13 Bindings for Analog Devices Industrial Ethernet PHYs
14
15allOf:
16 - $ref: ethernet-phy.yaml#
17
18properties:
19 adi,rx-internal-delay-ps:
20 description: |
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
23 enum: [ 1600, 1800, 2000, 2200, 2400 ]
24 default: 2000
25
26 adi,tx-internal-delay-ps:
27 description: |
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
30 enum: [ 1600, 1800, 2000, 2200, 2400 ]
31 default: 2000
32
33 adi,fifo-depth-bits:
34 description: |
35 When operating in RMII mode, this option configures the FIFO depth.
36 enum: [ 4, 8, 12, 16, 20, 24 ]
37 default: 8
38
6fdc6e23
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39unevaluatedProperties: false
40
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41examples:
42 - |
43 ethernet {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 phy-mode = "rgmii-id";
48
49 ethernet-phy@0 {
50 reg = <0>;
51
52 adi,rx-internal-delay-ps = <1800>;
53 adi,tx-internal-delay-ps = <2200>;
54 };
55 };
56 - |
57 ethernet {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 phy-mode = "rmii";
62
63 ethernet-phy@1 {
64 reg = <1>;
65
66 adi,fifo-depth-bits = <16>;
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67 };
68 };