]>
Commit | Line | Data |
---|---|---|
2eb32b0a M |
1 | TI SoC Ethernet Switch Controller Device Tree Bindings |
2 | ------------------------------------------------------ | |
3 | ||
4 | Required properties: | |
472204fe M |
5 | - compatible : Should be one of the below:- |
6 | "ti,cpsw" for backward compatible | |
7 | "ti,am335x-cpsw" for AM335x controllers | |
8 | "ti,am4372-cpsw" for AM437x controllers | |
9 | "ti,dra7-cpsw" for DRA7x controllers | |
2eb32b0a M |
10 | - reg : physical base address and size of the cpsw |
11 | registers map | |
12 | - interrupts : property with a value describing the interrupt | |
13 | number | |
2eb32b0a | 14 | - cpdma_channels : Specifies number of channels in CPDMA |
2eb32b0a | 15 | - ale_entries : Specifies No of entries ALE can hold |
2eb32b0a | 16 | - bd_ram_size : Specifies internal descriptor RAM size |
2eb32b0a M |
17 | - mac_control : Specifies Default MAC control register content |
18 | for the specific platform | |
19 | - slaves : Specifies number for slaves | |
e86ac13b M |
20 | - active_slave : Specifies the slave to use for time stamping, |
21 | ethtool and SIOCGMIIPHY | |
10d7fac4 TL |
22 | - cpsw-phy-sel : Specifies the phandle to the CPSW phy mode selection |
23 | device. See also cpsw-phy-sel.txt for it's binding. | |
24 | Note that in legacy cases cpsw-phy-sel may be | |
ad57b785 GS |
25 | a child device instead of a phandle |
26 | (DEPRECATED, use phys property instead). | |
2eb32b0a M |
27 | |
28 | Optional properties: | |
29 | - ti,hwmods : Must be "cpgmac0" | |
d9ba8f9e | 30 | - dual_emac : Specifies Switch to act as Dual EMAC |
0ba517b1 MP |
31 | - syscon : Phandle to the system control device node, which is |
32 | the control module device of the am33x | |
1d147ccb M |
33 | - mode-gpios : Should be added if one/multiple gpio lines are |
34 | required to be driven so that cpsw data lines | |
35 | can be connected to the phy via selective mux. | |
36 | For example in dra72x-evm, pcf gpio has to be | |
37 | driven low so that cpsw slave 0 and phy data | |
38 | lines are connected via mux. | |
88f0f0b0 GS |
39 | - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds |
40 | - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds | |
41 | Mult and shift will be calculated basing on CPTS | |
42 | rftclk frequency if both cpts_clock_shift and | |
43 | cpts_clock_mult properties are not provided. | |
470d1474 M |
44 | |
45 | Slave Properties: | |
46 | Required properties: | |
e8f08ee0 | 47 | - phy-mode : See ethernet.txt file in the same directory |
ad57b785 | 48 | - phys : phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt) |
470d1474 M |
49 | |
50 | Optional properties: | |
d9ba8f9e | 51 | - dual_emac_res_vlan : Specifies VID to be used to segregate the ports |
a5d2cb3b | 52 | - phy_id : Specifies slave phy id (deprecated, use phy-handle) |
9e42f715 | 53 | - phy-handle : See ethernet.txt file in the same directory |
2eb32b0a | 54 | |
687e3d55 PŠ |
55 | The MAC address will be determined using the optional properties |
56 | defined in ethernet.txt. | |
57 | ||
1f71e8c9 MB |
58 | Slave sub-nodes: |
59 | - fixed-link : See fixed-link.txt file in the same directory | |
a5d2cb3b DR |
60 | |
61 | Note: Exactly one of phy_id, phy-handle, or fixed-link must be specified. | |
1f71e8c9 | 62 | |
2eb32b0a M |
63 | Note: "ti,hwmods" field is used to fetch the base address and irq |
64 | resources from TI, omap hwmod data base during device registration. | |
65 | Future plan is to migrate hwmod data base contents into device tree | |
66 | blob so that, all the required data will be used from device tree dts | |
67 | file. | |
68 | ||
69 | Examples: | |
70 | ||
afc3bca4 | 71 | mac: ethernet@4a100000 { |
2eb32b0a M |
72 | compatible = "ti,cpsw"; |
73 | reg = <0x4A100000 0x1000>; | |
74 | interrupts = <55 0x4>; | |
75 | interrupt-parent = <&intc>; | |
e07b94f1 | 76 | cpdma_channels = <8>; |
e07b94f1 | 77 | ale_entries = <1024>; |
e07b94f1 | 78 | bd_ram_size = <0x2000>; |
e07b94f1 M |
79 | rx_descs = <64>; |
80 | mac_control = <0x20>; | |
81 | slaves = <2>; | |
e86ac13b | 82 | active_slave = <0>; |
00ab94ee RC |
83 | cpts_clock_mult = <0x80000000>; |
84 | cpts_clock_shift = <29>; | |
0ba517b1 | 85 | syscon = <&cm>; |
10d7fac4 | 86 | cpsw-phy-sel = <&phy_sel>; |
e07b94f1 | 87 | cpsw_emac0: slave@0 { |
549985ee | 88 | phy_id = <&davinci_mdio>, <0>; |
c5ceea7a | 89 | phy-mode = "rgmii-txid"; |
e07b94f1 M |
90 | /* Filled in by U-Boot */ |
91 | mac-address = [ 00 00 00 00 00 00 ]; | |
ad57b785 | 92 | phys = <&phy_gmii_sel 1 0>; |
2eb32b0a | 93 | }; |
e07b94f1 | 94 | cpsw_emac1: slave@1 { |
549985ee | 95 | phy_id = <&davinci_mdio>, <1>; |
c5ceea7a | 96 | phy-mode = "rgmii-txid"; |
e07b94f1 M |
97 | /* Filled in by U-Boot */ |
98 | mac-address = [ 00 00 00 00 00 00 ]; | |
ad57b785 | 99 | phys = <&phy_gmii_sel 2 0>; |
2eb32b0a M |
100 | }; |
101 | }; | |
102 | ||
103 | (or) | |
afc3bca4 | 104 | mac: ethernet@4a100000 { |
2eb32b0a M |
105 | compatible = "ti,cpsw"; |
106 | ti,hwmods = "cpgmac0"; | |
e07b94f1 | 107 | cpdma_channels = <8>; |
e07b94f1 | 108 | ale_entries = <1024>; |
e07b94f1 | 109 | bd_ram_size = <0x2000>; |
e07b94f1 M |
110 | rx_descs = <64>; |
111 | mac_control = <0x20>; | |
112 | slaves = <2>; | |
e86ac13b | 113 | active_slave = <0>; |
00ab94ee RC |
114 | cpts_clock_mult = <0x80000000>; |
115 | cpts_clock_shift = <29>; | |
0ba517b1 | 116 | syscon = <&cm>; |
10d7fac4 | 117 | cpsw-phy-sel = <&phy_sel>; |
e07b94f1 | 118 | cpsw_emac0: slave@0 { |
549985ee | 119 | phy_id = <&davinci_mdio>, <0>; |
c5ceea7a | 120 | phy-mode = "rgmii-txid"; |
e07b94f1 M |
121 | /* Filled in by U-Boot */ |
122 | mac-address = [ 00 00 00 00 00 00 ]; | |
ad57b785 | 123 | phys = <&phy_gmii_sel 1 0>; |
2eb32b0a | 124 | }; |
e07b94f1 | 125 | cpsw_emac1: slave@1 { |
549985ee | 126 | phy_id = <&davinci_mdio>, <1>; |
c5ceea7a | 127 | phy-mode = "rgmii-txid"; |
e07b94f1 M |
128 | /* Filled in by U-Boot */ |
129 | mac-address = [ 00 00 00 00 00 00 ]; | |
ad57b785 | 130 | phys = <&phy_gmii_sel 2 0>; |
2eb32b0a | 131 | }; |
2eb32b0a | 132 | }; |