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d8704342 MR |
1 | # SPDX-License-Identifier: GPL-2.0 |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/net/ethernet-phy.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: Ethernet PHY Generic Binding | |
8 | ||
9 | maintainers: | |
10 | - Andrew Lunn <andrew@lunn.ch> | |
11 | - Florian Fainelli <f.fainelli@gmail.com> | |
12 | - Heiner Kallweit <hkallweit1@gmail.com> | |
13 | ||
14 | # The dt-schema tools will generate a select statement first by using | |
15 | # the compatible, and second by using the node name if any. In our | |
16 | # case, the node name is the one we want to match on, while the | |
17 | # compatible is optional. | |
18 | select: | |
19 | properties: | |
20 | $nodename: | |
21 | pattern: "^ethernet-phy(@[a-f0-9]+)?$" | |
22 | ||
23 | required: | |
24 | - $nodename | |
25 | ||
26 | properties: | |
27 | $nodename: | |
28 | pattern: "^ethernet-phy(@[a-f0-9]+)?$" | |
29 | ||
30 | compatible: | |
31 | oneOf: | |
32 | - const: ethernet-phy-ieee802.3-c22 | |
33 | description: PHYs that implement IEEE802.3 clause 22 | |
34 | - const: ethernet-phy-ieee802.3-c45 | |
35 | description: PHYs that implement IEEE802.3 clause 45 | |
36 | - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" | |
37 | description: | |
38 | If the PHY reports an incorrect ID (or none at all) then the | |
39 | compatible list may contain an entry with the correct PHY ID | |
40 | in the above form. | |
41 | The first group of digits is the 16 bit Phy Identifier 1 | |
42 | register, this is the chip vendor OUI bits 3:18. The | |
43 | second group of digits is the Phy Identifier 2 register, | |
44 | this is the chip vendor OUI bits 19:24, followed by 10 | |
45 | bits of a vendor specific ID. | |
c8322754 JJ |
46 | - items: |
47 | - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" | |
48 | - const: ethernet-phy-ieee802.3-c22 | |
d8704342 MR |
49 | - items: |
50 | - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" | |
51 | - const: ethernet-phy-ieee802.3-c45 | |
52 | ||
53 | reg: | |
54 | minimum: 0 | |
55 | maximum: 31 | |
56 | description: | |
57 | The ID number for the PHY. | |
58 | ||
59 | interrupts: | |
60 | maxItems: 1 | |
61 | ||
62 | max-speed: | |
63 | enum: | |
64 | - 10 | |
65 | - 100 | |
66 | - 1000 | |
67 | - 2500 | |
68 | - 5000 | |
69 | - 10000 | |
70 | - 20000 | |
71 | - 25000 | |
72 | - 40000 | |
73 | - 50000 | |
74 | - 56000 | |
75 | - 100000 | |
76 | - 200000 | |
77 | description: | |
78 | Maximum PHY supported speed in Mbits / seconds. | |
79 | ||
80 | broken-turn-around: | |
d69c6ddd | 81 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
82 | description: |
83 | If set, indicates the PHY device does not correctly release | |
f42ceca2 FF |
84 | the turn around line low at end of the control phase of the |
85 | MDIO transaction. | |
d8704342 MR |
86 | |
87 | enet-phy-lane-swap: | |
d69c6ddd | 88 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
89 | description: |
90 | If set, indicates the PHY will swap the TX/RX lanes to | |
91 | compensate for the board being designed with the lanes | |
92 | swapped. | |
93 | ||
94 | eee-broken-100tx: | |
d69c6ddd | 95 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
96 | description: |
97 | Mark the corresponding energy efficient ethernet mode as | |
98 | broken and request the ethernet to stop advertising it. | |
99 | ||
100 | eee-broken-1000t: | |
d69c6ddd | 101 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
102 | description: |
103 | Mark the corresponding energy efficient ethernet mode as | |
104 | broken and request the ethernet to stop advertising it. | |
105 | ||
106 | eee-broken-10gt: | |
d69c6ddd | 107 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
108 | description: |
109 | Mark the corresponding energy efficient ethernet mode as | |
110 | broken and request the ethernet to stop advertising it. | |
111 | ||
112 | eee-broken-1000kx: | |
d69c6ddd | 113 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
114 | description: |
115 | Mark the corresponding energy efficient ethernet mode as | |
116 | broken and request the ethernet to stop advertising it. | |
117 | ||
118 | eee-broken-10gkx4: | |
d69c6ddd | 119 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
120 | description: |
121 | Mark the corresponding energy efficient ethernet mode as | |
122 | broken and request the ethernet to stop advertising it. | |
123 | ||
124 | eee-broken-10gkr: | |
d69c6ddd | 125 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
126 | description: |
127 | Mark the corresponding energy efficient ethernet mode as | |
128 | broken and request the ethernet to stop advertising it. | |
129 | ||
130 | phy-is-integrated: | |
d69c6ddd | 131 | $ref: /schemas/types.yaml#/definitions/flag |
d8704342 MR |
132 | description: |
133 | If set, indicates that the PHY is integrated into the same | |
134 | physical package as the Ethernet MAC. If needed, muxers | |
135 | should be configured to ensure the integrated PHY is | |
136 | used. The absence of this property indicates the muxers | |
137 | should be configured so that the external PHY is used. | |
138 | ||
139 | resets: | |
140 | maxItems: 1 | |
141 | ||
142 | reset-names: | |
143 | const: phy | |
144 | ||
145 | reset-gpios: | |
146 | maxItems: 1 | |
147 | description: | |
148 | The GPIO phandle and specifier for the PHY reset signal. | |
149 | ||
150 | reset-assert-us: | |
151 | description: | |
152 | Delay after the reset was asserted in microseconds. If this | |
153 | property is missing the delay will be skipped. | |
154 | ||
155 | reset-deassert-us: | |
156 | description: | |
157 | Delay after the reset was deasserted in microseconds. If | |
158 | this property is missing the delay will be skipped. | |
159 | ||
fb3d8bcd | 160 | sfp: |
d69c6ddd | 161 | $ref: /schemas/types.yaml#/definitions/phandle |
fb3d8bcd RK |
162 | description: |
163 | Specifies a reference to a node representing a SFP cage. | |
164 | ||
9150069b DM |
165 | rx-internal-delay-ps: |
166 | description: | | |
167 | RGMII Receive PHY Clock Delay defined in pico seconds. This is used for | |
168 | PHY's that have configurable RX internal delays. If this property is | |
169 | present then the PHY applies the RX delay. | |
170 | ||
171 | tx-internal-delay-ps: | |
172 | description: | | |
173 | RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for | |
174 | PHY's that have configurable TX internal delays. If this property is | |
175 | present then the PHY applies the TX delay. | |
176 | ||
d8704342 MR |
177 | required: |
178 | - reg | |
d8704342 | 179 | |
6a0e321e RH |
180 | additionalProperties: true |
181 | ||
d8704342 MR |
182 | examples: |
183 | - | | |
184 | ethernet { | |
185 | #address-cells = <1>; | |
186 | #size-cells = <0>; | |
187 | ||
188 | ethernet-phy@0 { | |
189 | compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45"; | |
190 | interrupt-parent = <&PIC>; | |
191 | interrupts = <35 1>; | |
192 | reg = <0>; | |
193 | ||
194 | resets = <&rst 8>; | |
195 | reset-names = "phy"; | |
196 | reset-gpios = <&gpio1 4 1>; | |
197 | reset-assert-us = <1000>; | |
198 | reset-deassert-us = <2000>; | |
199 | }; | |
200 | }; |