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Commit | Line | Data |
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c156633f SS |
1 | * Renesas Electronics Ethernet AVB |
2 | ||
3 | This file provides information on what the device node for the Ethernet AVB | |
4 | interface contains. | |
5 | ||
6 | Required properties: | |
7 | - compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC. | |
af8002d3 SH |
8 | "renesas,etheravb-r8a7791" if the device is a part of R8A7791 SoC. |
9 | "renesas,etheravb-r8a7792" if the device is a part of R8A7792 SoC. | |
10 | "renesas,etheravb-r8a7793" if the device is a part of R8A7793 SoC. | |
c156633f | 11 | "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC. |
619f3bd2 | 12 | "renesas,etheravb-r8a7795" if the device is a part of R8A7795 SoC. |
ed2eb0fb | 13 | "renesas,etheravb-r8a7796" if the device is a part of R8A7796 SoC. |
0e874361 SH |
14 | "renesas,etheravb-rcar-gen2" for generic R-Car Gen 2 compatible interface. |
15 | "renesas,etheravb-rcar-gen3" for generic R-Car Gen 3 compatible interface. | |
16 | ||
17 | When compatible with the generic version, nodes must list the | |
18 | SoC-specific version corresponding to the platform first | |
19 | followed by the generic version. | |
20 | ||
c156633f | 21 | - reg: offset and length of (1) the register block and (2) the stream buffer. |
619f3bd2 KM |
22 | - interrupts: A list of interrupt-specifiers, one for each entry in |
23 | interrupt-names. | |
24 | If interrupt-names is not present, an interrupt specifier | |
25 | for a single muxed interrupt. | |
c156633f SS |
26 | - phy-mode: see ethernet.txt file in the same directory. |
27 | - phy-handle: see ethernet.txt file in the same directory. | |
28 | - #address-cells: number of address cells for the MDIO bus, must be equal to 1. | |
29 | - #size-cells: number of size cells on the MDIO bus, must be equal to 0. | |
30 | - clocks: clock phandle and specifier pair. | |
31 | - pinctrl-0: phandle, referring to a default pin configuration node. | |
32 | ||
33 | Optional properties: | |
34 | - interrupt-parent: the phandle for the interrupt controller that services | |
35 | interrupts for this device. | |
619f3bd2 | 36 | - interrupt-names: A list of interrupt names. |
ed2eb0fb | 37 | For the R8A779[56] SoCs this property is mandatory; |
619f3bd2 KM |
38 | it should include one entry per channel, named "ch%u", |
39 | where %u is the channel number ranging from 0 to 24. | |
40 | For other SoCs this property is optional; if present | |
41 | it should contain "mux" for a single muxed interrupt. | |
c156633f SS |
42 | - pinctrl-names: pin configuration state name ("default"). |
43 | - renesas,no-ether-link: boolean, specify when a board does not provide a proper | |
44 | AVB_LINK signal. | |
45 | - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is | |
46 | active-low instead of normal active-high. | |
47 | ||
48 | Example: | |
49 | ||
50 | ethernet@e6800000 { | |
0e874361 | 51 | compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3"; |
619f3bd2 | 52 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; |
c156633f | 53 | interrupt-parent = <&gic>; |
619f3bd2 KM |
54 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
55 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
56 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
57 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
58 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
59 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
60 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
61 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
62 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
63 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
64 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
65 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
66 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
67 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
68 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
69 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
70 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
71 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
72 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
73 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
74 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
75 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
76 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
77 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
78 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
79 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
80 | "ch4", "ch5", "ch6", "ch7", | |
81 | "ch8", "ch9", "ch10", "ch11", | |
82 | "ch12", "ch13", "ch14", "ch15", | |
83 | "ch16", "ch17", "ch18", "ch19", | |
84 | "ch20", "ch21", "ch22", "ch23", | |
85 | "ch24"; | |
705bcdda GU |
86 | clocks = <&cpg CPG_MOD 812>; |
87 | power-domains = <&cpg>; | |
619f3bd2 | 88 | phy-mode = "rgmii-id"; |
c156633f | 89 | phy-handle = <&phy0>; |
619f3bd2 | 90 | |
c156633f SS |
91 | pinctrl-0 = <ðer_pins>; |
92 | pinctrl-names = "default"; | |
93 | renesas,no-ether-link; | |
94 | #address-cells = <1>; | |
95 | #size-cells = <0>; | |
96 | ||
97 | phy0: ethernet-phy@0 { | |
619f3bd2 KM |
98 | rxc-skew-ps = <900>; |
99 | rxdv-skew-ps = <0>; | |
100 | rxd0-skew-ps = <0>; | |
101 | rxd1-skew-ps = <0>; | |
102 | rxd2-skew-ps = <0>; | |
103 | rxd3-skew-ps = <0>; | |
104 | txc-skew-ps = <900>; | |
105 | txen-skew-ps = <0>; | |
106 | txd0-skew-ps = <0>; | |
107 | txd1-skew-ps = <0>; | |
108 | txd2-skew-ps = <0>; | |
109 | txd3-skew-ps = <0>; | |
c156633f SS |
110 | reg = <0>; |
111 | interrupt-parent = <&gpio2>; | |
619f3bd2 | 112 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
c156633f SS |
113 | }; |
114 | }; |