]>
Commit | Line | Data |
---|---|---|
b331b8ef EG |
1 | # SPDX-License-Identifier: GPL-2.0 |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: "http://devicetree.org/schemas/net/rockchip-dwmac.yaml#" | |
5 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | |
6 | ||
7 | title: Rockchip 10/100/1000 Ethernet driver(GMAC) | |
8 | ||
9 | maintainers: | |
10 | - David Wu <david.wu@rock-chips.com> | |
11 | ||
12 | # We need a select here so we don't match all nodes with 'snps,dwmac' | |
13 | select: | |
14 | properties: | |
15 | compatible: | |
16 | contains: | |
17 | enum: | |
18 | - rockchip,px30-gmac | |
19 | - rockchip,rk3128-gmac | |
20 | - rockchip,rk3228-gmac | |
21 | - rockchip,rk3288-gmac | |
22 | - rockchip,rk3328-gmac | |
23 | - rockchip,rk3366-gmac | |
24 | - rockchip,rk3368-gmac | |
25 | - rockchip,rk3399-gmac | |
26 | - rockchip,rv1108-gmac | |
27 | required: | |
28 | - compatible | |
29 | ||
30 | allOf: | |
31 | - $ref: "snps,dwmac.yaml#" | |
32 | ||
33 | properties: | |
34 | compatible: | |
35 | items: | |
36 | - enum: | |
37 | - rockchip,px30-gmac | |
38 | - rockchip,rk3128-gmac | |
39 | - rockchip,rk3228-gmac | |
40 | - rockchip,rk3288-gmac | |
41 | - rockchip,rk3328-gmac | |
42 | - rockchip,rk3366-gmac | |
43 | - rockchip,rk3368-gmac | |
44 | - rockchip,rk3399-gmac | |
45 | - rockchip,rv1108-gmac | |
46 | ||
47 | clocks: | |
48 | minItems: 5 | |
49 | maxItems: 8 | |
50 | ||
51 | clock-names: | |
52 | contains: | |
53 | enum: | |
54 | - stmmaceth | |
55 | - mac_clk_tx | |
56 | - mac_clk_rx | |
57 | - aclk_mac | |
58 | - pclk_mac | |
59 | - clk_mac_ref | |
60 | - clk_mac_refout | |
61 | - clk_mac_speed | |
62 | ||
63 | clock_in_out: | |
64 | description: | |
65 | For RGMII, it must be "input", means main clock(125MHz) | |
66 | is not sourced from SoC's PLL, but input from PHY. | |
67 | For RMII, "input" means PHY provides the reference clock(50MHz), | |
68 | "output" means GMAC provides the reference clock. | |
69 | $ref: /schemas/types.yaml#/definitions/string | |
70 | enum: [input, output] | |
71 | ||
72 | rockchip,grf: | |
73 | description: The phandle of the syscon node for the general register file. | |
74 | $ref: /schemas/types.yaml#/definitions/phandle | |
75 | ||
76 | tx_delay: | |
77 | description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default. | |
78 | $ref: /schemas/types.yaml#/definitions/uint32 | |
79 | ||
80 | rx_delay: | |
81 | description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default. | |
82 | $ref: /schemas/types.yaml#/definitions/uint32 | |
83 | ||
84 | phy-supply: | |
85 | description: PHY regulator | |
86 | ||
87 | required: | |
88 | - compatible | |
89 | - clocks | |
90 | - clock-names | |
91 | ||
92 | unevaluatedProperties: false | |
93 | ||
94 | examples: | |
95 | - | | |
96 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
97 | #include <dt-bindings/clock/rk3288-cru.h> | |
98 | ||
99 | gmac: ethernet@ff290000 { | |
100 | compatible = "rockchip,rk3288-gmac"; | |
101 | reg = <0xff290000 0x10000>; | |
102 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
103 | interrupt-names = "macirq"; | |
104 | clocks = <&cru SCLK_MAC>, | |
105 | <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, | |
106 | <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, | |
107 | <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; | |
108 | clock-names = "stmmaceth", | |
109 | "mac_clk_rx", "mac_clk_tx", | |
110 | "clk_mac_ref", "clk_mac_refout", | |
111 | "aclk_mac", "pclk_mac"; | |
112 | assigned-clocks = <&cru SCLK_MAC>; | |
113 | assigned-clock-parents = <&ext_gmac>; | |
114 | ||
115 | rockchip,grf = <&grf>; | |
116 | phy-mode = "rgmii"; | |
117 | clock_in_out = "input"; | |
118 | tx_delay = <0x30>; | |
119 | rx_delay = <0x10>; | |
120 | }; |