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Commit | Line | Data |
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1b55d622 RJ |
1 | * Broadcom iProc PCIe controller with the platform bus interface |
2 | ||
3 | Required properties: | |
f29224ae RJ |
4 | - compatible: |
5 | "brcm,iproc-pcie" for the first generation of PAXB based controller, | |
6 | used in SoCs including NSP, Cygnus, NS2, and Pegasus | |
f7acf811 RJ |
7 | "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based |
8 | controllers, used in Stingray | |
f29224ae RJ |
9 | "brcm,iproc-pcie-paxc" for the first generation of PAXC based |
10 | controller, used in NS2 | |
11 | "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based | |
12 | controller, used in Stingray | |
13 | PAXB-based root complex is used for external endpoint devices. PAXC-based | |
14 | root complex is connected to emulated endpoint devices internal to the ASIC | |
1b55d622 RJ |
15 | - reg: base address and length of the PCIe controller I/O register space |
16 | - #interrupt-cells: set to <1> | |
17 | - interrupt-map-mask and interrupt-map, standard PCI properties to define the | |
18 | mapping of the PCIe interface to interrupt numbers | |
19 | - linux,pci-domain: PCI domain ID. Should be unique for each host controller | |
20 | - bus-range: PCI bus numbers covered | |
21 | - #address-cells: set to <3> | |
22 | - #size-cells: set to <2> | |
23 | - device_type: set to "pci" | |
24 | - ranges: ranges for the PCI memory and I/O regions | |
25 | ||
26 | Optional properties: | |
27 | - phys: phandle of the PCIe PHY device | |
28 | - phy-names: must be "pcie-phy" | |
f29224ae | 29 | - dma-coherent: present if DMA operations are coherent |
3589c66c RJ |
30 | - dma-ranges: Some PAXB-based root complexes do not have inbound mapping done |
31 | by the ASIC after power on reset. In this case, SW is required to configure | |
32 | the mapping, based on inbound memory regions specified by this property. | |
1b55d622 | 33 | |
8d0afa1a RJ |
34 | - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done |
35 | by the ASIC after power on reset. In this case, SW needs to configure it | |
36 | ||
37 | If the brcm,pcie-ob property is present, the following properties become | |
38 | effective: | |
39 | ||
40 | Required: | |
41 | - brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal | |
42 | address used by the iProc PCIe core (not the PCIe address) | |
8d0afa1a | 43 | |
c7bd4819 RJ |
44 | MSI support (optional): |
45 | ||
46 | For older platforms without MSI integrated in the GIC, iProc PCIe core provides | |
47 | an event queue based MSI support. The iProc MSI uses host memories to store | |
48 | MSI posted writes in the event queues | |
49 | ||
f29224ae RJ |
50 | On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used |
51 | ||
52 | - msi-map: Maps a Requester ID to an MSI controller and associated MSI | |
53 | sideband data | |
54 | ||
55 | - msi-parent: Link to the device node of the MSI controller, used when no MSI | |
56 | sideband data is passed between the iProc PCIe controller and the MSI | |
57 | controller | |
58 | ||
59 | Refer to the following binding documents for more detailed description on | |
60 | the use of 'msi-map' and 'msi-parent': | |
61 | Documentation/devicetree/bindings/pci/pci-msi.txt | |
62 | Documentation/devicetree/bindings/interrupt-controller/msi.txt | |
c7bd4819 RJ |
63 | |
64 | When the iProc event queue based MSI is used, one needs to define the | |
65 | following properties in the MSI device node: | |
66 | - compatible: Must be "brcm,iproc-msi" | |
67 | - msi-controller: claims itself as an MSI controller | |
68 | - interrupt-parent: Link to its parent interrupt device | |
69 | - interrupts: List of interrupt IDs from its parent interrupt device | |
70 | ||
71 | Optional properties: | |
72 | - brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that | |
73 | require the interrupt enable registers to be set explicitly to enable MSI | |
74 | ||
1b55d622 RJ |
75 | Example: |
76 | pcie0: pcie@18012000 { | |
77 | compatible = "brcm,iproc-pcie"; | |
78 | reg = <0x18012000 0x1000>; | |
79 | ||
80 | #interrupt-cells = <1>; | |
81 | interrupt-map-mask = <0 0 0 0>; | |
82 | interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; | |
83 | ||
84 | linux,pci-domain = <0>; | |
85 | ||
86 | bus-range = <0x00 0xff>; | |
87 | ||
88 | #address-cells = <3>; | |
89 | #size-cells = <2>; | |
90 | device_type = "pci"; | |
91 | ranges = <0x81000000 0 0 0x28000000 0 0x00010000 | |
92 | 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; | |
93 | ||
94 | phys = <&phy 0 5>; | |
95 | phy-names = "pcie-phy"; | |
8d0afa1a RJ |
96 | |
97 | brcm,pcie-ob; | |
8d0afa1a | 98 | brcm,pcie-ob-axi-offset = <0x00000000>; |
c7bd4819 RJ |
99 | |
100 | msi-parent = <&msi0>; | |
101 | ||
102 | /* iProc event queue based MSI */ | |
103 | msi0: msi@18012000 { | |
104 | compatible = "brcm,iproc-msi"; | |
105 | msi-controller; | |
106 | interrupt-parent = <&gic>; | |
107 | interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, | |
108 | <GIC_SPI 97 IRQ_TYPE_NONE>, | |
109 | <GIC_SPI 98 IRQ_TYPE_NONE>, | |
110 | <GIC_SPI 99 IRQ_TYPE_NONE>, | |
111 | }; | |
1b55d622 RJ |
112 | }; |
113 | ||
114 | pcie1: pcie@18013000 { | |
115 | compatible = "brcm,iproc-pcie"; | |
116 | reg = <0x18013000 0x1000>; | |
117 | ||
118 | #interrupt-cells = <1>; | |
119 | interrupt-map-mask = <0 0 0 0>; | |
120 | interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; | |
121 | ||
122 | linux,pci-domain = <1>; | |
123 | ||
124 | bus-range = <0x00 0xff>; | |
125 | ||
126 | #address-cells = <3>; | |
127 | #size-cells = <2>; | |
128 | device_type = "pci"; | |
129 | ranges = <0x81000000 0 0 0x48000000 0 0x00010000 | |
130 | 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; | |
131 | ||
132 | phys = <&phy 1 6>; | |
133 | phy-names = "pcie-phy"; | |
134 | }; |