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53126a2f 1* Synopsys Designware PCIe interface
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2
3Required properties:
1db823ee 4- compatible: should contain "snps,dw-pcie" to identify the core.
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5- reg: Should contain the configuration address space.
6- reg-names: Must be "config" for the PCIe configuration space.
7 (The old way of getting the configuration address space from "ranges"
8 is deprecated and should be avoided.)
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9- #address-cells: set to <3>
10- #size-cells: set to <2>
11- device_type: set to "pci"
12- ranges: ranges for the PCI memory and I/O regions
13- #interrupt-cells: set to <1>
14- interrupt-map-mask and interrupt-map: standard PCI properties
15 to define the mapping of the PCIe interface to interrupt
16 numbers.
df770162 17- num-lanes: number of lanes to use
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18
19Optional properties:
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20- num-lanes: number of lanes to use (this property should be specified unless
21 the link is brought already up in BIOS)
340cba60 22- reset-gpio: gpio pin number of power good signal
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23- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
24 specify this property, to keep backwards compatibility a range of 0x00-0xff
25 is assumed if not present)
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26- clocks: Must contain an entry for each entry in clock-names.
27 See ../clocks/clock-bindings.txt for details.
28- clock-names: Must include the following entries:
29 - "pcie"
30 - "pcie_bus"