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Commit | Line | Data |
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1db823ee LS |
1 | * Freescale i.MX6 PCIe interface |
2 | ||
96291d56 | 3 | This PCIe host controller is based on the Synopsys DesignWare PCIe IP |
1db823ee LS |
4 | and thus inherits all the common properties defined in designware-pcie.txt. |
5 | ||
6 | Required properties: | |
9b3fe679 AS |
7 | - compatible: |
8 | - "fsl,imx6q-pcie" | |
9 | - "fsl,imx6sx-pcie", | |
10 | - "fsl,imx6qp-pcie" | |
11 | - "fsl,imx7d-pcie" | |
e3c06cd0 | 12 | - reg: base address and length of the PCIe controller |
1db823ee LS |
13 | - interrupts: A list of interrupt outputs of the controller. Must contain an |
14 | entry for each entry in the interrupt-names property. | |
15 | - interrupt-names: Must include the following entries: | |
16 | - "msi": The interrupt that is asserted when an MSI is received | |
17 | - clock-names: Must include the following additional entries: | |
18 | - "pcie_phy" | |
19 | ||
28e3abe5 JW |
20 | Optional properties: |
21 | - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0 | |
22 | - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0 | |
23 | - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20 | |
24 | - fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127 | |
25 | - fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127 | |
a5fcec48 TH |
26 | - fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for |
27 | gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs | |
28 | do not meet gen2 jitter requirements and thus for gen2 capability a gen2 | |
29 | compliant clock generator should be used and configured. | |
3ea8529a PŠ |
30 | - reset-gpio: Should specify the GPIO for controlling the PCI bus device reset |
31 | signal. It's not polarity aware and defaults to active-low reset sequence | |
32 | (L=reset state, H=operation state). | |
33 | - reset-gpio-active-high: If present then the reset sequence using the GPIO | |
34 | specified in the "reset-gpio" property is reversed (H=reset state, | |
35 | L=operation state). | |
c26ebe98 QS |
36 | - vpcie-supply: Should specify the regulator in charge of PCIe port power. |
37 | The regulator will be enabled when initializing the PCIe host and | |
38 | disabled either as part of the init process or when shutting down the | |
39 | host. | |
28e3abe5 | 40 | |
e3c06cd0 CF |
41 | Additional required properties for imx6sx-pcie: |
42 | - clock names: Must include the following additional entries: | |
43 | - "pcie_inbound_axi" | |
e24b6b51 LC |
44 | - power-domains: Must be set to phandles pointing to the DISPLAY and |
45 | PCIE_PHY power domains | |
46 | - power-domain-names: Must be "pcie", "pcie_phy" | |
e3c06cd0 | 47 | |
9b3fe679 AS |
48 | Additional required properties for imx7d-pcie: |
49 | - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain | |
50 | - resets: Must contain phandles to PCIe-related reset lines exposed by SRC | |
51 | IP block | |
52 | - reset-names: Must contain the following entires: | |
53 | - "pciephy" | |
54 | - "apps" | |
3e3f50b1 | 55 | - "turnoff" |
9b3fe679 | 56 | |
1db823ee LS |
57 | Example: |
58 | ||
4c9847b7 | 59 | pcie@01000000 { |
1db823ee | 60 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; |
fcd17303 LS |
61 | reg = <0x01ffc000 0x04000>, |
62 | <0x01f00000 0x80000>; | |
63 | reg-names = "dbi", "config"; | |
1db823ee LS |
64 | #address-cells = <3>; |
65 | #size-cells = <2>; | |
66 | device_type = "pci"; | |
67 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 | |
68 | 0x81000000 0 0 0x01f80000 0 0x00010000 | |
69 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; | |
70 | num-lanes = <1>; | |
71 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
72 | interrupt-names = "msi"; | |
73 | #interrupt-cells = <1>; | |
74 | interrupt-map-mask = <0 0 0 0x7>; | |
75 | interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
76 | <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
77 | <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
78 | <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
79 | clocks = <&clks 144>, <&clks 206>, <&clks 189>; | |
80 | clock-names = "pcie", "pcie_bus", "pcie_phy"; | |
81 | }; |