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5930fe4e | 1 | HiSilicon Hip05 and Hip06 PCIe host bridge DT description |
500a1d9a ZW |
2 | |
3 | HiSilicon PCIe host controller is based on Designware PCI core. | |
4 | It shares common functions with PCIe Designware core driver and inherits | |
5 | common properties defined in | |
6 | Documentation/devicetree/bindings/pci/designware-pci.txt. | |
7 | ||
8 | Additional properties are described here: | |
9 | ||
5930fe4e GP |
10 | Required properties |
11 | - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie". | |
500a1d9a ZW |
12 | - reg: Should contain rc_dbi, config registers location and length. |
13 | - reg-names: Must include the following entries: | |
14 | "rc_dbi": controller configuration registers; | |
15 | "config": PCIe configuration space registers. | |
16 | - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts. | |
17 | - port-id: Should be 0, 1, 2 or 3. | |
18 | ||
19 | Optional properties: | |
20 | - status: Either "ok" or "disabled". | |
21 | - dma-coherent: Present if DMA operations are coherent. | |
22 | ||
5930fe4e | 23 | Hip05 Example (note that Hip06 is the same except compatible): |
500a1d9a ZW |
24 | pcie@0xb0080000 { |
25 | compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; | |
26 | reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>; | |
27 | reg-names = "rc_dbi", "config"; | |
28 | bus-range = <0 15>; | |
29 | msi-parent = <&its_pcie>; | |
30 | #address-cells = <3>; | |
31 | #size-cells = <2>; | |
32 | device_type = "pci"; | |
33 | dma-coherent; | |
34 | ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>; | |
35 | num-lanes = <8>; | |
36 | port-id = <1>; | |
332bea1a GU |
37 | #interrupt-cells = <1>; |
38 | interrupt-map-mask = <0xf800 0 0 7>; | |
39 | interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10 | |
40 | 0x0 0 0 2 &mbigen_pcie 2 11 | |
41 | 0x0 0 0 3 &mbigen_pcie 3 12 | |
42 | 0x0 0 0 4 &mbigen_pcie 4 13>; | |
500a1d9a ZW |
43 | status = "ok"; |
44 | }; | |
a2ec1996 DL |
45 | |
46 | HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description. | |
b9c1153f DL |
47 | |
48 | Some BIOSes place the host controller in a mode where it is ECAM | |
49 | compliant for all devices other than the root complex. In such cases, | |
50 | the host controller should be described as below. | |
51 | ||
a2ec1996 DL |
52 | The properties and their meanings are identical to those described in |
53 | host-generic-pci.txt except as listed below. | |
54 | ||
55 | Properties of the host controller node that differ from | |
56 | host-generic-pci.txt: | |
57 | ||
b9c1153f DL |
58 | - compatible : Must be "hisilicon,hip06-pcie-ecam", or |
59 | "hisilicon,hip07-pcie-ecam" | |
a2ec1996 DL |
60 | |
61 | - reg : Two entries: First the ECAM configuration space for any | |
62 | other bus underneath the root bus. Second, the base | |
63 | and size of the HiSilicon host bridge registers include | |
64 | the RC's own config space. | |
65 | ||
66 | Example: | |
67 | pcie0: pcie@a0090000 { | |
b9c1153f | 68 | compatible = "hisilicon,hip06-pcie-ecam"; |
a2ec1996 DL |
69 | reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */ |
70 | <0 0xa0090000 0 0x10000>; /* host bridge registers */ | |
71 | bus-range = <0 31>; | |
72 | msi-map = <0x0000 &its_dsa 0x0000 0x2000>; | |
73 | msi-map-mask = <0xffff>; | |
74 | #address-cells = <3>; | |
75 | #size-cells = <2>; | |
76 | device_type = "pci"; | |
77 | dma-coherent; | |
78 | ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000 | |
79 | 0x01000000 0 0 0 0xb7ff0000 0 0x10000>; | |
80 | #interrupt-cells = <1>; | |
81 | interrupt-map-mask = <0xf800 0 0 7>; | |
82 | interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 | |
83 | 0x0 0 0 2 &mbigen_pcie0 650 4 | |
84 | 0x0 0 0 3 &mbigen_pcie0 650 4 | |
85 | 0x0 0 0 4 &mbigen_pcie0 650 4>; | |
86 | status = "ok"; | |
87 | }; |