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301d2d87 LW |
1 | PCI bus bridges have standardized Device Tree bindings: |
2 | ||
3 | PCI Bus Binding to: IEEE Std 1275-1994 | |
5b71456f | 4 | http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf |
301d2d87 LW |
5 | |
6 | And for the interrupt mapping part: | |
7 | ||
8 | Open Firmware Recommended Practice: Interrupt Mapping | |
5b71456f | 9 | http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf |
2801f725 LS |
10 | |
11 | Additionally to the properties specified in the above standards a host bridge | |
12 | driver implementation may support the following properties: | |
13 | ||
14 | - linux,pci-domain: | |
15 | If present this property assigns a fixed PCI domain number to a host bridge, | |
16 | otherwise an unstable (across boots) unique number will be assigned. | |
17 | It is required to either not set this property at all or set it for all | |
18 | host bridges in the system, otherwise potentially conflicting domain numbers | |
19 | may be assigned to root buses behind different host bridges. The domain | |
20 | number for each host bridge in the system must be unique. | |
2fa39159 SL |
21 | - max-link-speed: |
22 | If present this property specifies PCI gen for link capability. Host | |
23 | drivers could add this as a strategy to avoid unnecessary operation for | |
24 | unsupported link speed, for instance, trying to do training for | |
25 | unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' | |
26 | for gen2, and '1' for gen1. Any other values are invalid. | |
badd9f19 JPB |
27 | |
28 | PCI-PCI Bridge properties | |
29 | ------------------------- | |
30 | ||
31 | PCIe root ports and switch ports may be described explicitly in the device | |
32 | tree, as children of the host bridge node. Even though those devices are | |
33 | discoverable by probing, it might be necessary to describe properties that | |
34 | aren't provided by standard PCIe capabilities. | |
35 | ||
36 | Required properties: | |
37 | ||
38 | - reg: | |
39 | Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994 | |
40 | document, it is a five-cell address encoded as (phys.hi phys.mid | |
41 | phys.lo size.hi size.lo). phys.hi should contain the device's BDF as | |
42 | 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero. | |
43 | ||
44 | The bus number is defined by firmware, through the standard bridge | |
45 | configuration mechanism. If this port is a switch port, then firmware | |
46 | allocates the bus number and writes it into the Secondary Bus Number | |
47 | register of the bridge directly above this port. Otherwise, the bus | |
48 | number of a root port is the first number in the bus-range property, | |
49 | defaulting to zero. | |
50 | ||
51 | If firmware leaves the ARI Forwarding Enable bit set in the bridge | |
52 | above this port, then phys.hi contains the 8-bit function number as | |
53 | 0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification | |
54 | recommends that firmware only leaves ARI enabled when it knows that the | |
55 | OS is ARI-aware. | |
56 | ||
57 | Optional properties: | |
58 | ||
59 | - external-facing: | |
60 | When present, the port is external-facing. All bridges and endpoints | |
61 | downstream of this port are external to the machine. The OS can, for | |
62 | example, use this information to identify devices that cannot be | |
63 | trusted with relaxed DMA protection, as users could easily attach | |
64 | malicious devices to this port. | |
65 | ||
66 | Example: | |
67 | ||
68 | pcie@10000000 { | |
69 | compatible = "pci-host-ecam-generic"; | |
70 | ... | |
71 | pcie@0008 { | |
72 | /* Root port 00:01.0 is external-facing */ | |
73 | reg = <0x00000800 0 0 0 0>; | |
74 | external-facing; | |
75 | }; | |
76 | }; |