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Commit | Line | Data |
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dcd19de3 DD |
1 | * AppliedMicro X-Gene v1 PCIe MSI controller |
2 | ||
3 | Required properties: | |
4 | ||
5 | - compatible: should be "apm,xgene1-msi" to identify | |
6 | X-Gene v1 PCIe MSI controller block. | |
7 | - msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node | |
8 | - reg: physical base address (0x79000000) and length (0x900000) for controller | |
9 | registers. These registers include the MSI termination address and data | |
10 | registers as well as the MSI interrupt status registers. | |
11 | - reg-names: not required | |
12 | - interrupts: A list of 16 interrupt outputs of the controller, starting from | |
13 | interrupt number 0x10 to 0x1f. | |
14 | - interrupt-names: not required | |
15 | ||
16 | Each PCIe node needs to have property msi-parent that points to msi controller node | |
17 | ||
18 | Examples: | |
19 | ||
20 | SoC DTSI: | |
21 | ||
22 | + MSI node: | |
23 | msi@79000000 { | |
24 | compatible = "apm,xgene1-msi"; | |
25 | msi-controller; | |
26 | reg = <0x00 0x79000000 0x0 0x900000>; | |
27 | interrupts = <0x0 0x10 0x4> | |
28 | <0x0 0x11 0x4> | |
29 | <0x0 0x12 0x4> | |
30 | <0x0 0x13 0x4> | |
31 | <0x0 0x14 0x4> | |
32 | <0x0 0x15 0x4> | |
33 | <0x0 0x16 0x4> | |
34 | <0x0 0x17 0x4> | |
35 | <0x0 0x18 0x4> | |
36 | <0x0 0x19 0x4> | |
37 | <0x0 0x1a 0x4> | |
38 | <0x0 0x1b 0x4> | |
39 | <0x0 0x1c 0x4> | |
40 | <0x0 0x1d 0x4> | |
41 | <0x0 0x1e 0x4> | |
42 | <0x0 0x1f 0x4>; | |
43 | }; | |
44 | ||
45 | + PCIe controller node with msi-parent property pointing to MSI node: | |
46 | pcie0: pcie@1f2b0000 { | |
47 | status = "disabled"; | |
48 | device_type = "pci"; | |
49 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
50 | #interrupt-cells = <1>; | |
51 | #size-cells = <2>; | |
52 | #address-cells = <3>; | |
53 | reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ | |
54 | 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
55 | reg-names = "csr", "cfg"; | |
56 | ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ | |
57 | 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ | |
58 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 | |
59 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
60 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
61 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 | |
62 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 | |
63 | 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 | |
64 | 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; | |
65 | dma-coherent; | |
66 | clocks = <&pcie0clk 0>; | |
67 | msi-parent= <&msi>; | |
68 | }; |