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1 | STMicroelectronics STi MIPHY365x PHY binding |
2 | ============================================ | |
3 | ||
4 | This binding describes a miphy device that is used to control PHY hardware | |
5 | for SATA and PCIe. | |
6 | ||
7 | Required properties (controller (parent) node): | |
8 | - compatible : Should be "st,miphy365x-phy" | |
63139885 PG |
9 | - st,syscfg : Phandle / integer array property. Phandle of sysconfig group |
10 | containing the miphy registers and integer array should contain | |
11 | an entry for each port sub-node, specifying the control | |
12 | register offset inside the sysconfig group. | |
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13 | |
14 | Required nodes : A sub-node is required for each channel the controller | |
15 | provides. Address range information including the usual | |
16 | 'reg' and 'reg-names' properties are used inside these | |
17 | nodes to describe the controller's topology. These nodes | |
18 | are translated by the driver's .xlate() function. | |
19 | ||
20 | Required properties (port (child) node): | |
21 | - #phy-cells : Should be 1 (See second example) | |
22 | Cell after port phandle is device type from: | |
23 | - MIPHY_TYPE_SATA | |
24 | - MIPHY_TYPE_PCI | |
25 | - reg : Address and length of register sets for each device in | |
26 | "reg-names" | |
27 | - reg-names : The names of the register addresses corresponding to the | |
28 | registers filled in "reg": | |
29 | - sata: For SATA devices | |
30 | - pcie: For PCIe devices | |
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31 | |
32 | Optional properties (port (child) node): | |
33 | - st,sata-gen : Generation of locally attached SATA IP. Expected values | |
34 | are {1,2,3). If not supplied generation 1 hardware will | |
35 | be expected | |
36 | - st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp) | |
37 | - st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp) | |
38 | ||
39 | Example: | |
40 | ||
41 | miphy365x_phy: miphy365x@fe382000 { | |
42 | compatible = "st,miphy365x-phy"; | |
63139885 | 43 | st,syscfg = <&syscfg_rear 0x824 0x828>; |
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44 | #address-cells = <1>; |
45 | #size-cells = <1>; | |
46 | ranges; | |
47 | ||
48 | phy_port0: port@fe382000 { | |
63139885 PG |
49 | reg = <0xfe382000 0x100>, <0xfe394000 0x100>; |
50 | reg-names = "sata", "pcie"; | |
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51 | #phy-cells = <1>; |
52 | st,sata-gen = <3>; | |
53 | }; | |
54 | ||
55 | phy_port1: port@fe38a000 { | |
63139885 | 56 | reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;; |
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57 | reg-names = "sata", "pcie", "syscfg"; |
58 | #phy-cells = <1>; | |
59 | st,pcie-tx-pol-inv; | |
60 | }; | |
61 | }; | |
62 | ||
63 | Specifying phy control of devices | |
64 | ================================= | |
65 | ||
66 | Device nodes should specify the configuration required in their "phys" | |
67 | property, containing a phandle to the phy port node and a device type. | |
68 | ||
69 | Example: | |
70 | ||
71 | #include <dt-bindings/phy/phy-miphy365x.h> | |
72 | ||
73 | sata0: sata@fe380000 { | |
74 | ... | |
75 | phys = <&phy_port0 MIPHY_TYPE_SATA>; | |
76 | ... | |
77 | }; |