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Commit | Line | Data |
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9c3b4430 CYT |
1 | Allwinner sun9i USB PHY |
2 | ----------------------- | |
3 | ||
4 | Required properties: | |
5 | - compatible : should be one of | |
6 | * allwinner,sun9i-a80-usb-phy | |
7 | - reg : a list of offset + length pairs | |
8 | - #phy-cells : from the generic phy bindings, must be 0 | |
9 | - phy_type : "hsic" for HSIC usage; | |
10 | other values or absence of this property indicates normal USB | |
11 | - clocks : phandle + clock specifier for the phy clocks | |
12 | - clock-names : depending on the "phy_type" property, | |
13 | * "phy" for normal USB | |
14 | * "hsic_480M", "hsic_12M" for HSIC | |
15 | - resets : a list of phandle + reset specifier pairs | |
16 | - reset-names : depending on the "phy_type" property, | |
17 | * "phy" for normal USB | |
18 | * "hsic" for HSIC | |
19 | ||
20 | Optional Properties: | |
21 | - phy-supply : from the generic phy bindings, a phandle to a regulator that | |
22 | provides power to VBUS. | |
23 | ||
24 | It is recommended to list all clocks and resets available. | |
25 | The driver will only use those matching the phy_type. | |
26 | ||
27 | Example: | |
48c926cd | 28 | usbphy1: phy@a01800 { |
9c3b4430 CYT |
29 | compatible = "allwinner,sun9i-a80-usb-phy"; |
30 | reg = <0x00a01800 0x4>; | |
31 | clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, | |
32 | <&usb_phy_clk 3>; | |
33 | clock-names = "hsic_480M", "hsic_12M", "phy"; | |
34 | resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; | |
35 | reset-names = "hsic", "phy"; | |
9c3b4430 CYT |
36 | #phy-cells = <0>; |
37 | }; |