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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale IMX8MN IOMUX Controller
8
9maintainers:
10 - Anson Huang <Anson.Huang@nxp.com>
11
12description:
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14 for common binding part and usage.
15
16properties:
17 compatible:
18 const: fsl,imx8mn-iomuxc
19
20 reg:
21 maxItems: 1
22
23# Client device subnode's properties
24patternProperties:
25 'grp$':
26 type: object
27 description:
28 Pinctrl node's client devices use subnodes for desired pin configuration.
29 Client device subnodes use below standard properties.
30
31 properties:
32 fsl,pins:
33 description:
34 each entry consists of 6 integers and represents the mux and config
35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
36 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
37 be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
39 refer to i.MX8M Nano Reference Manual for detailed CONFIG settings.
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40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
41 items:
42 items:
43 - description: |
44 "mux_reg" indicates the offset of mux register.
45 - description: |
46 "conf_reg" indicates the offset of pad configuration register.
47 - description: |
48 "input_reg" indicates the offset of select input register.
49 - description: |
50 "mux_val" indicates the mux value to be applied.
51 - description: |
52 "input_val" indicates the select input value to be applied.
53 - description: |
54 "pad_setting" indicates the pad configuration value to be applied.
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55
56 required:
57 - fsl,pins
58
59 additionalProperties: false
60
61required:
62 - compatible
63 - reg
64
65additionalProperties: false
66
67examples:
68 # Pinmux controller node
69 - |
70 iomuxc: pinctrl@30330000 {
71 compatible = "fsl,imx8mn-iomuxc";
72 reg = <0x30330000 0x10000>;
73
74 pinctrl_uart2: uart2grp {
75 fsl,pins =
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
78 };
79 };
80
81...