]>
Commit | Line | Data |
---|---|---|
463e270f TP |
1 | * Marvell Armada XP SoC pinctrl driver for mpp |
2 | ||
3 | Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding | |
4 | part and usage. | |
5 | ||
6 | Required properties: | |
7 | - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", | |
8 | "marvell,mv78460-pinctrl" | |
356ca6ce | 9 | - reg: register specifier of MPP registers |
463e270f TP |
10 | |
11 | This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460. | |
12 | ||
13 | Available mpp pins/groups and functions: | |
14 | Note: brackets (x) are not part of the mpp name for marvell,function and given | |
15 | only for more detailed description in this document. | |
16 | ||
17 | * Marvell Armada XP (all variants) | |
18 | ||
19 | name pins functions | |
20 | ================================================================================ | |
a361cbc5 | 21 | mpp0 0 gpio, ge0(txclkout), lcd(d0) |
463e270f TP |
22 | mpp1 1 gpio, ge0(txd0), lcd(d1) |
23 | mpp2 2 gpio, ge0(txd1), lcd(d2) | |
24 | mpp3 3 gpio, ge0(txd2), lcd(d3) | |
25 | mpp4 4 gpio, ge0(txd3), lcd(d4) | |
26 | mpp5 5 gpio, ge0(txctl), lcd(d5) | |
27 | mpp6 6 gpio, ge0(rxd0), lcd(d6) | |
28 | mpp7 7 gpio, ge0(rxd1), lcd(d7) | |
29 | mpp8 8 gpio, ge0(rxd2), lcd(d8) | |
30 | mpp9 9 gpio, ge0(rxd3), lcd(d9) | |
31 | mpp10 10 gpio, ge0(rxctl), lcd(d10) | |
32 | mpp11 11 gpio, ge0(rxclk), lcd(d11) | |
a361cbc5 | 33 | mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) |
88b355f1 TP |
34 | mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13) |
35 | mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15) | |
f1b2db90 | 36 | mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) |
88b355f1 TP |
37 | mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16) |
38 | mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17) | |
463e270f TP |
39 | mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) |
40 | mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) | |
41 | mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) | |
100dc5d8 | 42 | mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat) |
463e270f TP |
43 | mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) |
44 | mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) | |
bc99357f TP |
45 | mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) |
46 | mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) | |
80b3d04f | 47 | mpp26 26 gpio, lcd(clk), tdm(fsync) |
463e270f TP |
48 | mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) |
49 | mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) | |
80b3d04f | 50 | mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) |
463e270f | 51 | mpp30 30 gpio, tdm(int1), sd0(clk) |
80b3d04f TP |
52 | mpp31 31 gpio, tdm(int2), sd0(cmd) |
53 | mpp32 32 gpio, tdm(int3), sd0(d0) | |
b19bf379 TP |
54 | mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) |
55 | mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) | |
463e270f | 56 | mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) |
50a7d13d TP |
57 | mpp36 36 gpio, spi0(mosi) |
58 | mpp37 37 gpio, spi0(miso) | |
59 | mpp38 38 gpio, spi0(sck) | |
60 | mpp39 39 gpio, spi0(cs0) | |
88b355f1 TP |
61 | mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), |
62 | spi1(cs1) | |
50a7d13d | 63 | mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), |
88b355f1 | 64 | pcie(clkreq1), spi1(cs2) |
dae5597f | 65 | mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) |
88b355f1 TP |
66 | mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), |
67 | spi1(cs3) | |
50a7d13d | 68 | mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), |
88b355f1 TP |
69 | dram(bat), spi1(cs4) |
70 | mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), | |
b19bf379 | 71 | spi1(cs5), dram(vttctrl) |
88b355f1 TP |
72 | mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), |
73 | spi1(cs6) | |
50a7d13d | 74 | mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), |
88b355f1 | 75 | ref(clkout), spi1(cs7) |
fb53b61d | 76 | mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb) |
463e270f TP |
77 | |
78 | * Marvell Armada XP (mv78260 and mv78460 only) | |
79 | ||
80 | name pins functions | |
81 | ================================================================================ | |
82 | mpp49 49 gpio, dev(we3) | |
83 | mpp50 50 gpio, dev(we2) | |
84 | mpp51 51 gpio, dev(ad16) | |
85 | mpp52 52 gpio, dev(ad17) | |
86 | mpp53 53 gpio, dev(ad18) | |
87 | mpp54 54 gpio, dev(ad19) | |
80b3d04f TP |
88 | mpp55 55 gpio, dev(ad20) |
89 | mpp56 56 gpio, dev(ad21) | |
90 | mpp57 57 gpio, dev(ad22) | |
463e270f TP |
91 | mpp58 58 gpio, dev(ad23) |
92 | mpp59 59 gpio, dev(ad24) | |
93 | mpp60 60 gpio, dev(ad25) | |
94 | mpp61 61 gpio, dev(ad26) | |
95 | mpp62 62 gpio, dev(ad27) | |
96 | mpp63 63 gpio, dev(ad28) | |
97 | mpp64 64 gpio, dev(ad29) | |
98 | mpp65 65 gpio, dev(ad30) | |
99 | mpp66 66 gpio, dev(ad31) |