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be306dac TR |
1 | Device tree binding for NVIDIA Tegra XUSB pad controller |
2 | ======================================================== | |
3 | ||
b1accd10 TR |
4 | NOTE: It turns out that this binding isn't an accurate description of the XUSB |
5 | pad controller. While the description is good enough for the functional subset | |
6 | required for PCIe and SATA, it lacks the flexibility to represent the features | |
7 | needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt. | |
8 | The binding described in this file is deprecated and should not be used. | |
9 | ||
be306dac TR |
10 | The Tegra XUSB pad controller manages a set of lanes, each of which can be |
11 | assigned to one out of a set of different pads. Some of these pads have an | |
12 | associated PHY that must be powered up before the pad can be used. | |
13 | ||
14 | This document defines the device-specific binding for the XUSB pad controller. | |
15 | ||
16 | Refer to pinctrl-bindings.txt in this directory for generic information about | |
17 | pin controller device tree bindings and ../phy/phy-bindings.txt for details on | |
18 | how to describe and reference PHYs in device trees. | |
19 | ||
20 | Required properties: | |
21 | -------------------- | |
193c9d23 PW |
22 | - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl". |
23 | Otherwise, must contain '"nvidia,<chip>-xusb-padctl", | |
24 | "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210. | |
be306dac TR |
25 | - reg: Physical base address and length of the controller's registers. |
26 | - resets: Must contain an entry for each entry in reset-names. | |
27 | See ../reset/reset.txt for details. | |
28 | - reset-names: Must include the following entries: | |
29 | - padctl | |
30 | - #phy-cells: Should be 1. The specifier is the index of the PHY to reference. | |
31 | See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values. | |
32 | ||
33 | Lane muxing: | |
34 | ------------ | |
35 | ||
36 | Child nodes contain the pinmux configurations following the conventions from | |
37 | the pinctrl-bindings.txt document. Typically a single, static configuration is | |
38 | given and applied at boot time. | |
39 | ||
40 | Each subnode describes groups of lanes along with parameters and pads that | |
41 | they should be assigned to. The name of these subnodes is not important. All | |
42 | subnodes should be parsed solely based on their content. | |
43 | ||
44 | Each subnode only applies the parameters that are explicitly listed. In other | |
45 | words, if a subnode that lists a function but no pin configuration parameters | |
46 | implies no information about any pin configuration parameters. Similarly, a | |
47 | subnode that describes only an IDDQ parameter implies no information about | |
48 | what function the pins are assigned to. For this reason even seemingly boolean | |
49 | values are actually tristates in this binding: unspecified, off or on. | |
50 | Unspecified is represented as an absent property, and off/on are represented | |
51 | as integer values 0 and 1. | |
52 | ||
53 | Required properties: | |
54 | - nvidia,lanes: An array of strings. Each string is the name of a lane. | |
55 | ||
56 | Optional properties: | |
57 | - nvidia,function: A string that is the name of the function (pad) that the | |
58 | pin or group should be assigned to. Valid values for function names are | |
59 | listed below. | |
60 | - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) | |
61 | ||
62 | Note that not all of these properties are valid for all lanes. Lanes can be | |
63 | divided into three groups: | |
64 | ||
65 | - otg-0, otg-1, otg-2: | |
66 | ||
67 | Valid functions for this group are: "snps", "xusb", "uart", "rsvd". | |
68 | ||
69 | The nvidia,iddq property does not apply to this group. | |
70 | ||
71 | - ulpi-0, hsic-0, hsic-1: | |
72 | ||
73 | Valid functions for this group are: "snps", "xusb". | |
74 | ||
75 | The nvidia,iddq property does not apply to this group. | |
76 | ||
77 | - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: | |
78 | ||
79 | Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". | |
80 | ||
81 | ||
82 | Example: | |
83 | ======== | |
84 | ||
85 | SoC file extract: | |
86 | ----------------- | |
87 | ||
f43521e9 | 88 | padctl@7009f000 { |
be306dac TR |
89 | compatible = "nvidia,tegra124-xusb-padctl"; |
90 | reg = <0x0 0x7009f000 0x0 0x1000>; | |
91 | resets = <&tegra_car 142>; | |
92 | reset-names = "padctl"; | |
93 | ||
94 | #phy-cells = <1>; | |
95 | }; | |
96 | ||
97 | Board file extract: | |
98 | ------------------- | |
99 | ||
48c926cd | 100 | pcie-controller@1003000 { |
be306dac TR |
101 | ... |
102 | ||
103 | phys = <&padctl 0>; | |
104 | phy-names = "pcie"; | |
105 | ||
106 | ... | |
107 | }; | |
108 | ||
109 | ... | |
110 | ||
f43521e9 | 111 | padctl: padctl@7009f000 { |
be306dac TR |
112 | pinctrl-0 = <&padctl_default>; |
113 | pinctrl-names = "default"; | |
114 | ||
115 | padctl_default: pinmux { | |
116 | usb3 { | |
117 | nvidia,lanes = "pcie-0", "pcie-1"; | |
118 | nvidia,function = "usb3"; | |
119 | nvidia,iddq = <0>; | |
120 | }; | |
121 | ||
122 | pcie { | |
123 | nvidia,lanes = "pcie-2", "pcie-3", | |
124 | "pcie-4"; | |
125 | nvidia,function = "pcie"; | |
126 | nvidia,iddq = <0>; | |
127 | }; | |
128 | ||
129 | sata { | |
130 | nvidia,lanes = "sata-0"; | |
131 | nvidia,function = "sata"; | |
132 | nvidia,iddq = <0>; | |
133 | }; | |
134 | }; | |
135 | }; |