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Commit | Line | Data |
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b31d100e | 1 | Qualcomm MSM8974 TLMM block |
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2 | |
3 | Required properties: | |
893a7d11 | 4 | - compatible: "qcom,msm8974-pinctrl" |
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5 | - reg: Should be the base address and length of the TLMM block. |
6 | - interrupts: Should be the parent IRQ of the TLMM block. | |
7 | - interrupt-controller: Marks the device node as an interrupt controller. | |
8 | - #interrupt-cells: Should be two. | |
9 | - gpio-controller: Marks the device node as a GPIO controller. | |
10 | - #gpio-cells : Should be two. | |
11 | The first cell is the gpio pin number and the | |
12 | second cell is used for optional parameters. | |
13 | ||
14 | Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for | |
15 | a general description of GPIO and interrupt bindings. | |
16 | ||
17 | Please refer to pinctrl-bindings.txt in this directory for details of the | |
18 | common pinctrl bindings used by client devices, including the meaning of the | |
19 | phrase "pin configuration node". | |
20 | ||
a0e27f51 | 21 | Qualcomm's pin configuration nodes act as a container for an arbitrary number of |
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22 | subnodes. Each of these subnodes represents some desired configuration for a |
23 | pin, a group, or a list of pins or groups. This configuration can include the | |
24 | mux function to select on those pin(s)/group(s), and various pin configuration | |
25 | parameters, such as pull-up, drive strength, etc. | |
26 | ||
27 | The name of each subnode is not important; all subnodes should be enumerated | |
28 | and processed purely based on their content. | |
29 | ||
30 | Each subnode only affects those parameters that are explicitly listed. In | |
31 | other words, a subnode that lists a mux function but no pin configuration | |
32 | parameters implies no information about any pin configuration parameters. | |
33 | Similarly, a pin subnode that describes a pullup parameter implies no | |
34 | information about e.g. the mux function. | |
35 | ||
36 | ||
37 | The following generic properties as defined in pinctrl-bindings.txt are valid | |
38 | to specify in a pin configuration subnode: | |
39 | pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength. | |
40 | ||
41 | Non-empty subnodes must specify the 'pins' property. | |
42 | Note that not all properties are valid for all pins. | |
43 | ||
44 | ||
893a7d11 | 45 | Valid values for pins are: |
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46 | gpio0-gpio145 |
47 | Supports mux, bias and drive-strength | |
48 | ||
49 | sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data | |
50 | Supports bias and drive-strength | |
51 | ||
893a7d11 | 52 | Valid values for function are: |
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53 | cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm, |
54 | blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, | |
55 | blsp_uim2, blsp_uart2, blsp_i2c2, blsp_spi2, | |
56 | blsp_uim3, blsp_uart3, blsp_i2c3, blsp_spi3, | |
57 | blsp_uim4, blsp_uart4, blsp_i2c4, blsp_spi4, | |
58 | blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5, | |
59 | blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6, | |
60 | blsp_uim7, blsp_uart7, blsp_i2c7, blsp_spi7, | |
61 | blsp_uim8, blsp_uart8, blsp_i2c8, blsp_spi8, | |
62 | blsp_uim9, blsp_uart9, blsp_i2c9, blsp_spi9, | |
63 | blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10, | |
64 | blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11, | |
65 | blsp_uim12, blsp_uart12, blsp_i2c12, blsp_spi12, | |
66 | blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2 | |
67 | blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, | |
68 | sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1, | |
69 | cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2, | |
70 | cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, | |
71 | hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, | |
72 | gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s, | |
144ef626 | 73 | ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, gpio |
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74 | |
75 | (Note that this is not yet the complete list of functions) | |
76 | ||
77 | ||
78 | ||
79 | Example: | |
80 | ||
81 | msmgpio: pinctrl@fd510000 { | |
b31d100e | 82 | compatible = "qcom,msm8974-pinctrl"; |
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83 | reg = <0xfd510000 0x4000>; |
84 | ||
85 | gpio-controller; | |
86 | #gpio-cells = <2>; | |
87 | interrupt-controller; | |
88 | #interrupt-cells = <2>; | |
89 | interrupts = <0 208 0>; | |
90 | ||
91 | pinctrl-names = "default"; | |
92 | pinctrl-0 = <&uart2_default>; | |
93 | ||
94 | uart2_default: uart2_default { | |
95 | mux { | |
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96 | pins = "gpio4", "gpio5"; |
97 | function = "blsp_uart2"; | |
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98 | }; |
99 | ||
100 | tx { | |
893a7d11 | 101 | pins = "gpio4"; |
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102 | drive-strength = <4>; |
103 | bias-disable; | |
104 | }; | |
105 | ||
106 | rx { | |
893a7d11 | 107 | pins = "gpio5"; |
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108 | drive-strength = <2>; |
109 | bias-pull-up; | |
110 | }; | |
111 | }; | |
112 | }; |