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Commit | Line | Data |
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43059f6b BA |
1 | Qualcomm PMIC GPIO block |
2 | ||
3 | This binding describes the GPIO block(s) found in the 8xxx series of | |
4 | PMIC's from Qualcomm. | |
5 | ||
6 | - compatible: | |
7 | Usage: required | |
8 | Value type: <string> | |
9 | Definition: must be one of: | |
96b0686d | 10 | "qcom,pm8005-gpio" |
43059f6b BA |
11 | "qcom,pm8018-gpio" |
12 | "qcom,pm8038-gpio" | |
13 | "qcom,pm8058-gpio" | |
7414b099 | 14 | "qcom,pm8916-gpio" |
43059f6b BA |
15 | "qcom,pm8917-gpio" |
16 | "qcom,pm8921-gpio" | |
17 | "qcom,pm8941-gpio" | |
016c2f4d | 18 | "qcom,pm8994-gpio" |
96b0686d | 19 | "qcom,pm8998-gpio" |
43059f6b | 20 | "qcom,pma8084-gpio" |
5fdd1a6a | 21 | "qcom,pmi8994-gpio" |
697818f3 | 22 | "qcom,pmi8998-gpio" |
ed80f6eb | 23 | "qcom,pms405-gpio" |
43059f6b | 24 | |
647dbd1e SB |
25 | And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" |
26 | if the device is on an spmi bus or an ssbi bus respectively | |
27 | ||
43059f6b BA |
28 | - reg: |
29 | Usage: required | |
30 | Value type: <prop-encoded-array> | |
31 | Definition: Register base of the GPIO block and length. | |
32 | ||
33 | - interrupts: | |
34 | Usage: required | |
35 | Value type: <prop-encoded-array> | |
36 | Definition: Must contain an array of encoded interrupt specifiers for | |
37 | each available GPIO | |
38 | ||
39 | - gpio-controller: | |
40 | Usage: required | |
41 | Value type: <none> | |
42 | Definition: Mark the device node as a GPIO controller | |
43 | ||
44 | - #gpio-cells: | |
45 | Usage: required | |
46 | Value type: <u32> | |
47 | Definition: Must be 2; | |
48 | the first cell will be used to define gpio number and the | |
49 | second denotes the flags for this gpio | |
50 | ||
51 | Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for | |
52 | a general description of GPIO and interrupt bindings. | |
53 | ||
54 | Please refer to pinctrl-bindings.txt in this directory for details of the | |
55 | common pinctrl bindings used by client devices, including the meaning of the | |
56 | phrase "pin configuration node". | |
57 | ||
58 | The pin configuration nodes act as a container for an arbitrary number of | |
59 | subnodes. Each of these subnodes represents some desired configuration for a | |
60 | pin or a list of pins. This configuration can include the | |
61 | mux function to select on those pin(s), and various pin configuration | |
62 | parameters, as listed below. | |
63 | ||
64 | ||
65 | SUBNODES: | |
66 | ||
67 | The name of each subnode is not important; all subnodes should be enumerated | |
68 | and processed purely based on their content. | |
69 | ||
70 | Each subnode only affects those parameters that are explicitly listed. In | |
71 | other words, a subnode that lists a mux function but no pin configuration | |
72 | parameters implies no information about any pin configuration parameters. | |
73 | Similarly, a pin subnode that describes a pullup parameter implies no | |
74 | information about e.g. the mux function. | |
75 | ||
76 | The following generic properties as defined in pinctrl-bindings.txt are valid | |
77 | to specify in a pin configuration subnode: | |
78 | ||
79 | - pins: | |
80 | Usage: required | |
81 | Value type: <string-array> | |
82 | Definition: List of gpio pins affected by the properties specified in | |
83 | this subnode. Valid pins are: | |
96b0686d | 84 | gpio1-gpio4 for pm8005 |
43059f6b BA |
85 | gpio1-gpio6 for pm8018 |
86 | gpio1-gpio12 for pm8038 | |
87 | gpio1-gpio40 for pm8058 | |
7414b099 | 88 | gpio1-gpio4 for pm8916 |
43059f6b BA |
89 | gpio1-gpio38 for pm8917 |
90 | gpio1-gpio44 for pm8921 | |
91 | gpio1-gpio36 for pm8941 | |
016c2f4d | 92 | gpio1-gpio22 for pm8994 |
96b0686d | 93 | gpio1-gpio26 for pm8998 |
43059f6b | 94 | gpio1-gpio22 for pma8084 |
5fdd1a6a | 95 | gpio1-gpio10 for pmi8994 |
89444dad | 96 | gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) |
43059f6b BA |
97 | |
98 | - function: | |
99 | Usage: required | |
100 | Value type: <string> | |
101 | Definition: Specify the alternative function to be configured for the | |
102 | specified pins. Valid values are: | |
103 | "normal", | |
104 | "paired", | |
105 | "func1", | |
106 | "func2", | |
107 | "dtest1", | |
108 | "dtest2", | |
109 | "dtest3", | |
d7b5f5cc FW |
110 | "dtest4", |
111 | And following values are supported by LV/MV GPIO subtypes: | |
112 | "func3", | |
113 | "func4" | |
43059f6b BA |
114 | |
115 | - bias-disable: | |
116 | Usage: optional | |
117 | Value type: <none> | |
118 | Definition: The specified pins should be configured as no pull. | |
119 | ||
120 | - bias-pull-down: | |
121 | Usage: optional | |
122 | Value type: <none> | |
123 | Definition: The specified pins should be configured as pull down. | |
124 | ||
125 | - bias-pull-up: | |
126 | Usage: optional | |
127 | Value type: <empty> | |
128 | Definition: The specified pins should be configured as pull up. | |
129 | ||
130 | - qcom,pull-up-strength: | |
131 | Usage: optional | |
132 | Value type: <u32> | |
133 | Definition: Specifies the strength to use for pull up, if selected. | |
134 | Valid values are; as defined in | |
135 | <dt-bindings/pinctrl/qcom,pmic-gpio.h>: | |
136 | 1: 30uA (PMIC_GPIO_PULL_UP_30) | |
137 | 2: 1.5uA (PMIC_GPIO_PULL_UP_1P5) | |
138 | 3: 31.5uA (PMIC_GPIO_PULL_UP_31P5) | |
139 | 4: 1.5uA + 30uA boost (PMIC_GPIO_PULL_UP_1P5_30) | |
4e99a3bd | 140 | If this property is omitted 30uA strength will be used if |
43059f6b BA |
141 | pull up is selected |
142 | ||
143 | - bias-high-impedance: | |
144 | Usage: optional | |
145 | Value type: <none> | |
146 | Definition: The specified pins will put in high-Z mode and disabled. | |
147 | ||
148 | - input-enable: | |
149 | Usage: optional | |
150 | Value type: <none> | |
151 | Definition: The specified pins are put in input mode. | |
152 | ||
153 | - output-high: | |
154 | Usage: optional | |
155 | Value type: <none> | |
156 | Definition: The specified pins are configured in output mode, driven | |
157 | high. | |
158 | ||
159 | - output-low: | |
160 | Usage: optional | |
161 | Value type: <none> | |
162 | Definition: The specified pins are configured in output mode, driven | |
163 | low. | |
164 | ||
165 | - power-source: | |
166 | Usage: optional | |
167 | Value type: <u32> | |
168 | Definition: Selects the power source for the specified pins. Valid | |
169 | power sources are defined per chip in | |
170 | <dt-bindings/pinctrl/qcom,pmic-gpio.h> | |
171 | ||
172 | - qcom,drive-strength: | |
173 | Usage: optional | |
174 | Value type: <u32> | |
175 | Definition: Selects the drive strength for the specified pins. Value | |
176 | drive strengths are: | |
177 | 0: no (PMIC_GPIO_STRENGTH_NO) | |
178 | 1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V | |
179 | 2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V | |
180 | 3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V | |
181 | as defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h> | |
182 | ||
183 | - drive-push-pull: | |
184 | Usage: optional | |
185 | Value type: <none> | |
186 | Definition: The specified pins are configured in push-pull mode. | |
187 | ||
188 | - drive-open-drain: | |
189 | Usage: optional | |
190 | Value type: <none> | |
191 | Definition: The specified pins are configured in open-drain mode. | |
192 | ||
193 | - drive-open-source: | |
194 | Usage: optional | |
195 | Value type: <none> | |
196 | Definition: The specified pins are configured in open-source mode. | |
197 | ||
d7b5f5cc FW |
198 | - qcom,analog-pass: |
199 | Usage: optional | |
200 | Value type: <none> | |
201 | Definition: The specified pins are configured in analog-pass-through mode. | |
202 | ||
203 | - qcom,atest: | |
204 | Usage: optional | |
205 | Value type: <u32> | |
206 | Definition: Selects ATEST rail to route to GPIO when it's configured | |
207 | in analog-pass-through mode. | |
208 | Valid values are 1-4 corresponding to ATEST1 to ATEST4. | |
209 | ||
223463fc FW |
210 | - qcom,dtest-buffer: |
211 | Usage: optional | |
212 | Value type: <u32> | |
213 | Definition: Selects DTEST rail to route to GPIO when it's configured | |
214 | as digital input. | |
215 | Valid values are 1-4 corresponding to DTEST1 to DTEST4. | |
216 | ||
43059f6b BA |
217 | Example: |
218 | ||
219 | pm8921_gpio: gpio@150 { | |
647dbd1e | 220 | compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio"; |
43059f6b BA |
221 | reg = <0x150 0x160>; |
222 | interrupts = <192 1>, <193 1>, <194 1>, | |
223 | <195 1>, <196 1>, <197 1>, | |
224 | <198 1>, <199 1>, <200 1>, | |
225 | <201 1>, <202 1>, <203 1>, | |
226 | <204 1>, <205 1>, <206 1>, | |
227 | <207 1>, <208 1>, <209 1>, | |
228 | <210 1>, <211 1>, <212 1>, | |
229 | <213 1>, <214 1>, <215 1>, | |
230 | <216 1>, <217 1>, <218 1>, | |
231 | <219 1>, <220 1>, <221 1>, | |
232 | <222 1>, <223 1>, <224 1>, | |
233 | <225 1>, <226 1>, <227 1>, | |
234 | <228 1>, <229 1>, <230 1>, | |
235 | <231 1>, <232 1>, <233 1>, | |
236 | <234 1>, <235 1>; | |
237 | ||
238 | gpio-controller; | |
239 | #gpio-cells = <2>; | |
240 | ||
241 | pm8921_gpio_keys: gpio-keys { | |
242 | volume-keys { | |
243 | pins = "gpio20", "gpio21"; | |
244 | function = "normal"; | |
245 | ||
246 | input-enable; | |
247 | bias-pull-up; | |
248 | drive-push-pull; | |
249 | qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; | |
250 | power-source = <PM8921_GPIO_S4>; | |
251 | }; | |
252 | }; | |
253 | }; |