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1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-pinctrl.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: Qualcomm Technologies, Inc. SC8180X TLMM block | |
8 | ||
9 | maintainers: | |
10 | - Bjorn Andersson <bjorn.andersson@linaro.org> | |
11 | ||
12 | description: | | |
13 | This binding describes the Top Level Mode Multiplexer block found in the | |
14 | SC8180X platform. | |
15 | ||
16 | allOf: | |
17 | - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# | |
18 | ||
19 | properties: | |
20 | compatible: | |
21 | const: qcom,sc8180x-tlmm | |
22 | ||
23 | reg: | |
24 | maxItems: 3 | |
25 | ||
26 | reg-names: | |
27 | items: | |
28 | - const: "west" | |
29 | - const: "east" | |
30 | - const: "south" | |
31 | ||
32 | interrupts: true | |
33 | interrupt-controller: true | |
34 | '#interrupt-cells': true | |
35 | gpio-controller: true | |
36 | gpio-reserved-ranges: true | |
37 | '#gpio-cells': true | |
38 | gpio-ranges: true | |
39 | wakeup-parent: true | |
40 | ||
41 | required: | |
42 | - compatible | |
43 | - reg | |
44 | - reg-names | |
45 | ||
46 | additionalProperties: false | |
47 | ||
48 | patternProperties: | |
49 | '-state$': | |
50 | oneOf: | |
51 | - $ref: "#/$defs/qcom-sc8180x-tlmm-state" | |
52 | - patternProperties: | |
53 | ".*": | |
54 | $ref: "#/$defs/qcom-sc8180x-tlmm-state" | |
55 | ||
56 | '$defs': | |
57 | qcom-sc8180x-tlmm-state: | |
58 | type: object | |
59 | description: | |
60 | Pinctrl node's client devices use subnodes for desired pin configuration. | |
61 | Client device subnodes use below standard properties. | |
62 | $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" | |
63 | ||
64 | properties: | |
65 | pins: | |
66 | description: | |
67 | List of gpio pins affected by the properties specified in this | |
68 | subnode. | |
69 | items: | |
70 | oneOf: | |
71 | - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$" | |
72 | - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] | |
73 | minItems: 1 | |
74 | maxItems: 16 | |
75 | ||
76 | function: | |
77 | description: | |
78 | Specify the alternative function to be configured for the specified | |
79 | pins. | |
80 | ||
81 | enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens, | |
82 | atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3, | |
83 | atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async, | |
84 | cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, | |
85 | cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8, | |
86 | cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot, | |
87 | dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2, | |
88 | gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s, | |
89 | hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync, | |
90 | mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, | |
91 | mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, | |
92 | pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset, | |
93 | pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink, | |
94 | qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs, | |
95 | qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, | |
96 | qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, | |
97 | qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4, | |
98 | sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu, | |
99 | tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, | |
100 | usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger, | |
101 | wlan1_adc, wlan2_adc, wmss_reset ] | |
102 | ||
103 | bias-disable: true | |
104 | bias-pull-down: true | |
105 | bias-pull-up: true | |
106 | drive-strength: true | |
107 | input-enable: true | |
108 | output-high: true | |
109 | output-low: true | |
110 | ||
111 | required: | |
112 | - pins | |
113 | - function | |
114 | ||
115 | additionalProperties: false | |
116 | ||
117 | examples: | |
118 | - | | |
119 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
120 | pinctrl@3100000 { | |
121 | compatible = "qcom,sc8180x-tlmm"; | |
122 | reg = <0x03100000 0x300000>, | |
123 | <0x03500000 0x700000>, | |
124 | <0x03d00000 0x300000>; | |
125 | reg-names = "west", "east", "south"; | |
126 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
127 | gpio-controller; | |
128 | #gpio-cells = <2>; | |
129 | interrupt-controller; | |
130 | #interrupt-cells = <2>; | |
131 | gpio-ranges = <&tlmm 0 0 190>; | |
132 | ||
133 | gpio-wo-subnode-state { | |
134 | pins = "gpio1"; | |
135 | function = "gpio"; | |
136 | }; | |
137 | ||
138 | uart-w-subnodes-state { | |
139 | rx { | |
140 | pins = "gpio4"; | |
141 | function = "qup6"; | |
142 | bias-pull-up; | |
143 | }; | |
144 | ||
145 | tx { | |
146 | pins = "gpio5"; | |
147 | function = "qup6"; | |
148 | bias-disable; | |
149 | }; | |
150 | }; | |
151 | }; | |
152 | ... |