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d3e51161 HS |
1 | * Rockchip Pinmux Controller |
2 | ||
3 | The Rockchip Pinmux Controller, enables the IC | |
4 | to share one PAD to several functional blocks. The sharing is done by | |
f3ababa8 DA |
5 | multiplexing the PAD input/output signals. For each PAD there are several |
6 | muxing options with option 0 being the use as a GPIO. | |
d3e51161 HS |
7 | |
8 | Please refer to pinctrl-bindings.txt in this directory for details of the | |
9 | common pinctrl bindings used by client devices, including the meaning of the | |
10 | phrase "pin configuration node". | |
11 | ||
12 | The Rockchip pin configuration node is a node of a group of pins which can be | |
13 | used for a specific device or function. This node represents both mux and | |
14 | config of the pins in that group. The 'pins' selects the function mode(also | |
15 | named pin mode) this pin can work on and the 'config' configures various pad | |
16 | settings such as pull-up, etc. | |
17 | ||
18 | The pins are grouped into up to 5 individual pin banks which need to be | |
19 | defined as gpio sub-nodes of the pinmux controller. | |
20 | ||
21 | Required properties for iomux controller: | |
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22 | - compatible: should be |
23 | "rockchip,rv1108-pinctrl": for Rockchip RV1108 | |
24 | "rockchip,rk2928-pinctrl": for Rockchip RK2928 | |
25 | "rockchip,rk3066a-pinctrl": for Rockchip RK3066a | |
26 | "rockchip,rk3066b-pinctrl": for Rockchip RK3066b | |
d23c66df | 27 | "rockchip,rk3128-pinctrl": for Rockchip RK3128 |
ab714cfb AY |
28 | "rockchip,rk3188-pinctrl": for Rockchip RK3188 |
29 | "rockchip,rk3228-pinctrl": for Rockchip RK3228 | |
30 | "rockchip,rk3288-pinctrl": for Rockchip RK3288 | |
31 | "rockchip,rk3328-pinctrl": for Rockchip RK3328 | |
32 | "rockchip,rk3368-pinctrl": for Rockchip RK3368 | |
33 | "rockchip,rk3399-pinctrl": for Rockchip RK3399 | |
34 | ||
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35 | - rockchip,grf: phandle referencing a syscon providing the |
36 | "general register files" | |
37 | ||
38 | Optional properties for iomux controller: | |
39 | - rockchip,pmu: phandle referencing a syscon providing the pmu registers | |
40 | as some SoCs carry parts of the iomux controller registers there. | |
daecdc66 HS |
41 | Required for at least rk3188 and rk3288. On the rk3368 this should |
42 | point to the PMUGRF syscon. | |
c51426ef HS |
43 | |
44 | Deprecated properties for iomux controller: | |
6ca5274d | 45 | - reg: first element is the general register space of the iomux controller |
bfc7a42a | 46 | It should be large enough to contain also separate pull registers. |
c51426ef HS |
47 | second element is the separate pull register space of the rk3188. |
48 | Use rockchip,grf and rockchip,pmu described above instead. | |
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49 | |
50 | Required properties for gpio sub nodes: | |
fc72c923 | 51 | - compatible: "rockchip,gpio-bank" |
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52 | - reg: register of the gpio bank (different than the iomux registerset) |
53 | - interrupts: base interrupt of the gpio bank in the interrupt controller | |
54 | - clocks: clock that drives this bank | |
55 | - gpio-controller: identifies the node as a gpio controller and pin bank. | |
56 | - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO | |
57 | binding is used, the amount of cells must be specified as 2. See generic | |
58 | GPIO binding documentation for description of particular cells. | |
59 | - interrupt-controller: identifies the controller node as interrupt-parent. | |
60 | - #interrupt-cells: the value of this property should be 2 and the interrupt | |
61 | cells should use the standard two-cell scheme described in | |
62 | bindings/interrupt-controller/interrupts.txt | |
63 | ||
c51426ef | 64 | Deprecated properties for gpio sub nodes: |
fc72c923 | 65 | - compatible: "rockchip,rk3188-gpio-bank0" |
c51426ef HS |
66 | - reg: second element: separate pull register for rk3188 bank0, use |
67 | rockchip,pmu described above instead | |
68 | ||
d3e51161 HS |
69 | Required properties for pin configuration node: |
70 | - rockchip,pins: 3 integers array, represents a group of pins mux and config | |
71 | setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. | |
f3ababa8 | 72 | The MUX 0 means gpio and MUX 1 to N mean the specific device function. |
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73 | The phandle of a node containing the generic pinconfig options |
74 | to use, as described in pinctrl-bindings.txt in this directory. | |
75 | ||
76 | Examples: | |
77 | ||
78 | #include <dt-bindings/pinctrl/rockchip.h> | |
79 | ||
80 | ... | |
81 | ||
82 | pinctrl@20008000 { | |
83 | compatible = "rockchip,rk3066a-pinctrl"; | |
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84 | rockchip,grf = <&grf>; |
85 | ||
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86 | #address-cells = <1>; |
87 | #size-cells = <1>; | |
88 | ranges; | |
89 | ||
90 | gpio0: gpio0@20034000 { | |
91 | compatible = "rockchip,gpio-bank"; | |
92 | reg = <0x20034000 0x100>; | |
93 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
94 | clocks = <&clk_gates8 9>; | |
95 | ||
96 | gpio-controller; | |
97 | #gpio-cells = <2>; | |
98 | ||
99 | interrupt-controller; | |
100 | #interrupt-cells = <2>; | |
101 | }; | |
102 | ||
103 | ... | |
104 | ||
105 | pcfg_pull_default: pcfg_pull_default { | |
106 | bias-pull-pin-default | |
107 | }; | |
108 | ||
109 | uart2 { | |
110 | uart2_xfer: uart2-xfer { | |
111 | rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>, | |
112 | <RK_GPIO1 9 1 &pcfg_pull_default>; | |
113 | }; | |
114 | }; | |
115 | }; | |
116 | ||
117 | uart2: serial@20064000 { | |
118 | compatible = "snps,dw-apb-uart"; | |
119 | reg = <0x20064000 0x400>; | |
120 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
121 | reg-shift = <2>; | |
122 | reg-io-width = <1>; | |
123 | clocks = <&mux_uart2>; | |
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124 | |
125 | pinctrl-names = "default"; | |
126 | pinctrl-0 = <&uart2_xfer>; | |
127 | }; | |
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128 | |
129 | Example for rk3188: | |
130 | ||
131 | pinctrl@20008000 { | |
132 | compatible = "rockchip,rk3188-pinctrl"; | |
c51426ef HS |
133 | rockchip,grf = <&grf>; |
134 | rockchip,pmu = <&pmu>; | |
6ca5274d HS |
135 | #address-cells = <1>; |
136 | #size-cells = <1>; | |
137 | ranges; | |
138 | ||
4c9847b7 | 139 | gpio0: gpio0@2000a000 { |
6ca5274d | 140 | compatible = "rockchip,rk3188-gpio-bank0"; |
c51426ef | 141 | reg = <0x2000a000 0x100>; |
6ca5274d HS |
142 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
143 | clocks = <&clk_gates8 9>; | |
144 | ||
145 | gpio-controller; | |
146 | #gpio-cells = <2>; | |
147 | ||
148 | interrupt-controller; | |
149 | #interrupt-cells = <2>; | |
150 | }; | |
151 | ||
4c9847b7 | 152 | gpio1: gpio1@2003c000 { |
6ca5274d HS |
153 | compatible = "rockchip,gpio-bank"; |
154 | reg = <0x2003c000 0x100>; | |
155 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
156 | clocks = <&clk_gates8 10>; | |
157 | ||
158 | gpio-controller; | |
159 | #gpio-cells = <2>; | |
160 | ||
161 | interrupt-controller; | |
162 | #interrupt-cells = <2>; | |
163 | }; | |
164 | ||
165 | ... | |
166 | ||
167 | }; |