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b053dc5a KG |
1 | 4xx/Axon EMAC ethernet nodes |
2 | ||
3 | The EMAC ethernet controller in IBM and AMCC 4xx chips, and also | |
f884ab15 | 4 | the Axon bridge. To operate this needs to interact with a this |
b053dc5a KG |
5 | special McMAL DMA controller, and sometimes an RGMII or ZMII |
6 | interface. In addition to the nodes and properties described | |
7 | below, the node for the OPB bus on which the EMAC sits must have a | |
8 | correct clock-frequency property. | |
9 | ||
10 | i) The EMAC node itself | |
11 | ||
12 | Required properties: | |
13 | - device_type : "network" | |
14 | ||
15 | - compatible : compatible list, contains 2 entries, first is | |
16 | "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, | |
17 | 405gp, Axon) and second is either "ibm,emac" or | |
18 | "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", | |
19 | "ibm,emac4" | |
20 | - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> | |
21 | - interrupt-parent : optional, if needed for interrupt mapping | |
22 | - reg : <registers mapping> | |
23 | - local-mac-address : 6 bytes, MAC address | |
24 | - mal-device : phandle of the associated McMAL node | |
25 | - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated | |
26 | with this EMAC | |
27 | - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated | |
28 | with this EMAC | |
29 | - cell-index : 1 cell, hardware index of the EMAC cell on a given | |
30 | ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on | |
31 | each Axon chip) | |
32 | - max-frame-size : 1 cell, maximum frame size supported in bytes | |
33 | - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec | |
34 | operations. | |
35 | For Axon, 2048 | |
36 | - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec | |
37 | operations. | |
38 | For Axon, 2048. | |
39 | - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate | |
40 | thresholds). | |
41 | For Axon, 0x00000010 | |
42 | - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) | |
43 | in bytes. | |
44 | For Axon, 0x00000100 (I think ...) | |
45 | - phy-mode : string, mode of operations of the PHY interface. | |
46 | Supported values are: "mii", "rmii", "smii", "rgmii", | |
47 | "tbi", "gmii", rtbi", "sgmii". | |
48 | For Axon on CAB, it is "rgmii" | |
49 | - mdio-device : 1 cell, required iff using shared MDIO registers | |
50 | (440EP). phandle of the EMAC to use to drive the | |
51 | MDIO lines for the PHY used by this EMAC. | |
52 | - zmii-device : 1 cell, required iff connected to a ZMII. phandle of | |
53 | the ZMII device node | |
54 | - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII | |
55 | channel or 0xffffffff if ZMII is only used for MDIO. | |
56 | - rgmii-device : 1 cell, required iff connected to an RGMII. phandle | |
57 | of the RGMII device node. | |
58 | For Axon: phandle of plb5/plb4/opb/rgmii | |
59 | - rgmii-channel : 1 cell, required iff connected to an RGMII. Which | |
60 | RGMII channel is used by this EMAC. | |
61 | Fox Axon: present, whatever value is appropriate for each | |
62 | EMAC, that is the content of the current (bogus) "phy-port" | |
63 | property. | |
64 | ||
65 | Optional properties: | |
66 | - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, | |
67 | a search is performed. | |
68 | - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY | |
69 | for, used if phy-address is absent. bit 0x00000001 is | |
70 | MDIO address 0. | |
71 | For Axon it can be absent, though my current driver | |
72 | doesn't handle phy-address yet so for now, keep | |
73 | 0x00ffffff in it. | |
a3a4a816 CL |
74 | - phy-handle : Used to describe configurations where a external PHY |
75 | is used. Please refer to: | |
76 | Documentation/devicetree/bindings/net/ethernet.txt | |
b053dc5a KG |
77 | - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec |
78 | operations (if absent the value is the same as | |
79 | rx-fifo-size). For Axon, either absent or 2048. | |
80 | - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec | |
81 | operations (if absent the value is the same as | |
82 | tx-fifo-size). For Axon, either absent or 2048. | |
83 | - tah-device : 1 cell, optional. If connected to a TAH engine for | |
84 | offload, phandle of the TAH device node. | |
85 | - tah-channel : 1 cell, optional. If appropriate, channel used on the | |
86 | TAH engine. | |
a3a4a816 CL |
87 | - fixed-link : Fixed-link subnode describing a link to a non-MDIO |
88 | managed entity. See | |
89 | Documentation/devicetree/bindings/net/fixed-link.txt | |
90 | for details. | |
91 | - mdio subnode : When the EMAC has a phy connected to its local | |
92 | mdio, which us supported by the kernel's network | |
93 | PHY library in drivers/net/phy, there must be device | |
94 | tree subnode with the following required properties: | |
95 | - #address-cells: Must be <1>. | |
96 | - #size-cells: Must be <0>. | |
b053dc5a | 97 | |
a3a4a816 CL |
98 | For PHY definitions: Please refer to |
99 | Documentation/devicetree/bindings/net/phy.txt and | |
100 | Documentation/devicetree/bindings/net/ethernet.txt | |
101 | ||
102 | Examples: | |
b053dc5a KG |
103 | |
104 | EMAC0: ethernet@40000800 { | |
105 | device_type = "network"; | |
106 | compatible = "ibm,emac-440gp", "ibm,emac"; | |
107 | interrupt-parent = <&UIC1>; | |
108 | interrupts = <1c 4 1d 4>; | |
109 | reg = <40000800 70>; | |
110 | local-mac-address = [00 04 AC E3 1B 1E]; | |
111 | mal-device = <&MAL0>; | |
112 | mal-tx-channel = <0 1>; | |
113 | mal-rx-channel = <0>; | |
114 | cell-index = <0>; | |
115 | max-frame-size = <5dc>; | |
116 | rx-fifo-size = <1000>; | |
117 | tx-fifo-size = <800>; | |
118 | phy-mode = "rmii"; | |
119 | phy-map = <00000001>; | |
120 | zmii-device = <&ZMII0>; | |
121 | zmii-channel = <0>; | |
122 | }; | |
123 | ||
a3a4a816 CL |
124 | EMAC1: ethernet@ef600c00 { |
125 | device_type = "network"; | |
126 | compatible = "ibm,emac-apm821xx", "ibm,emac4sync"; | |
127 | interrupt-parent = <&EMAC1>; | |
128 | interrupts = <0 1>; | |
129 | #interrupt-cells = <1>; | |
130 | #address-cells = <0>; | |
131 | #size-cells = <0>; | |
132 | interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */ | |
133 | 1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>; | |
134 | reg = <0xef600c00 0x000000c4>; | |
135 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ | |
136 | mal-device = <&MAL0>; | |
137 | mal-tx-channel = <0>; | |
138 | mal-rx-channel = <0>; | |
139 | cell-index = <0>; | |
140 | max-frame-size = <9000>; | |
141 | rx-fifo-size = <16384>; | |
142 | tx-fifo-size = <2048>; | |
143 | fifo-entry-size = <10>; | |
144 | phy-mode = "rgmii"; | |
145 | phy-handle = <&phy0>; | |
146 | phy-map = <0x00000000>; | |
147 | rgmii-device = <&RGMII0>; | |
148 | rgmii-channel = <0>; | |
149 | tah-device = <&TAH0>; | |
150 | tah-channel = <0>; | |
151 | has-inverted-stacr-oc; | |
152 | has-new-stacr-staopc; | |
153 | ||
154 | mdio { | |
155 | #address-cells = <1>; | |
156 | #size-cells = <0>; | |
157 | ||
158 | phy0: ethernet-phy@0 { | |
159 | compatible = "ethernet-phy-ieee802.3-c22"; | |
160 | reg = <0>; | |
161 | }; | |
162 | }; | |
163 | }; | |
164 | ||
165 | ||
b053dc5a KG |
166 | ii) McMAL node |
167 | ||
168 | Required properties: | |
169 | - device_type : "dma-controller" | |
170 | - compatible : compatible list, containing 2 entries, first is | |
171 | "ibm,mcmal-CHIP" where CHIP is the host ASIC (like | |
172 | emac) and the second is either "ibm,mcmal" or | |
173 | "ibm,mcmal2". | |
174 | For Axon, "ibm,mcmal-axon","ibm,mcmal2" | |
175 | - interrupts : <interrupt mapping for the MAL interrupts sources: | |
176 | 5 sources: tx_eob, rx_eob, serr, txde, rxde>. | |
177 | For Axon: This is _different_ from the current | |
178 | firmware. We use the "delayed" interrupts for txeob | |
179 | and rxeob. Thus we end up with mapping those 5 MPIC | |
180 | interrupts, all level positive sensitive: 10, 11, 32, | |
181 | 33, 34 (in decimal) | |
182 | - dcr-reg : < DCR registers range > | |
183 | - dcr-parent : if needed for dcr-reg | |
184 | - num-tx-chans : 1 cell, number of Tx channels | |
185 | - num-rx-chans : 1 cell, number of Rx channels | |
186 | ||
187 | iii) ZMII node | |
188 | ||
189 | Required properties: | |
190 | - compatible : compatible list, containing 2 entries, first is | |
191 | "ibm,zmii-CHIP" where CHIP is the host ASIC (like | |
192 | EMAC) and the second is "ibm,zmii". | |
193 | For Axon, there is no ZMII node. | |
194 | - reg : <registers mapping> | |
195 | ||
196 | iv) RGMII node | |
197 | ||
198 | Required properties: | |
199 | - compatible : compatible list, containing 2 entries, first is | |
200 | "ibm,rgmii-CHIP" where CHIP is the host ASIC (like | |
201 | EMAC) and the second is "ibm,rgmii". | |
202 | For Axon, "ibm,rgmii-axon","ibm,rgmii" | |
203 | - reg : <registers mapping> | |
204 | - revision : as provided by the RGMII new version register if | |
205 | available. | |
206 | For Axon: 0x0000012a |