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1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
2 | # Copyright (C) 2020 SiFive, Inc. | |
3 | %YAML 1.2 | |
4 | --- | |
5 | $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# | |
6 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
7 | ||
8 | title: SiFive L2 Cache Controller | |
9 | ||
10 | maintainers: | |
11 | - Sagar Kadam <sagar.kadam@sifive.com> | |
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12 | - Paul Walmsley <paul.walmsley@sifive.com> |
13 | ||
14 | description: | |
15 | The SiFive Level 2 Cache Controller is used to provide access to fast copies | |
16 | of memory for masters in a Core Complex. The Level 2 Cache Controller also | |
17 | acts as directory-based coherency manager. | |
18 | All the properties in ePAPR/DeviceTree specification applies for this platform. | |
19 | ||
20 | allOf: | |
21 | - $ref: /schemas/cache-controller.yaml# | |
22 | ||
23 | select: | |
24 | properties: | |
25 | compatible: | |
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26 | contains: |
27 | enum: | |
28 | - sifive,fu540-c000-ccache | |
29 | - sifive,fu740-c000-ccache | |
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30 | |
31 | required: | |
32 | - compatible | |
33 | ||
34 | properties: | |
35 | compatible: | |
36 | items: | |
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37 | - enum: |
38 | - sifive,fu540-c000-ccache | |
39 | - sifive,fu740-c000-ccache | |
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40 | - const: cache |
41 | ||
42 | cache-block-size: | |
43 | const: 64 | |
44 | ||
45 | cache-level: | |
46 | const: 2 | |
47 | ||
48 | cache-sets: | |
b60cf8e5 | 49 | enum: [1024, 2048] |
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50 | |
51 | cache-size: | |
52 | const: 2097152 | |
53 | ||
54 | cache-unified: true | |
55 | ||
56 | interrupts: | |
993dcfac | 57 | minItems: 3 |
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58 | items: |
59 | - description: DirError interrupt | |
60 | - description: DataError interrupt | |
61 | - description: DataFail interrupt | |
62 | - description: DirFail interrupt | |
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63 | |
64 | reg: | |
65 | maxItems: 1 | |
66 | ||
67 | next-level-cache: true | |
68 | ||
69 | memory-region: | |
0499220d | 70 | maxItems: 1 |
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71 | description: | |
72 | The reference to the reserved-memory for the L2 Loosely Integrated Memory region. | |
73 | The reserved memory node should be defined as per the bindings in reserved-memory.txt. | |
74 | ||
af951c3a YS |
75 | if: |
76 | properties: | |
77 | compatible: | |
78 | contains: | |
79 | const: sifive,fu540-c000-ccache | |
80 | ||
81 | then: | |
82 | properties: | |
83 | interrupts: | |
84 | description: | | |
85 | Must contain entries for DirError, DataError and DataFail signals. | |
86 | maxItems: 3 | |
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87 | cache-sets: |
88 | const: 1024 | |
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89 | |
90 | else: | |
91 | properties: | |
92 | interrupts: | |
93 | description: | | |
94 | Must contain entries for DirError, DataError, DataFail, DirFail signals. | |
95 | minItems: 4 | |
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96 | cache-sets: |
97 | const: 2048 | |
af951c3a | 98 | |
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99 | additionalProperties: false |
100 | ||
101 | required: | |
102 | - compatible | |
103 | - cache-block-size | |
104 | - cache-level | |
105 | - cache-sets | |
106 | - cache-size | |
107 | - cache-unified | |
108 | - interrupts | |
109 | - reg | |
110 | ||
111 | examples: | |
112 | - | | |
113 | cache-controller@2010000 { | |
114 | compatible = "sifive,fu540-c000-ccache", "cache"; | |
115 | cache-block-size = <64>; | |
116 | cache-level = <2>; | |
117 | cache-sets = <1024>; | |
118 | cache-size = <2097152>; | |
119 | cache-unified; | |
120 | reg = <0x2010000 0x1000>; | |
121 | interrupt-parent = <&plic0>; | |
122 | interrupts = <1>, | |
123 | <2>, | |
124 | <3>; | |
125 | next-level-cache = <&L25>; | |
126 | memory-region = <&l2_lim>; | |
127 | }; |