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859e4280 SH |
1 | MediaTek SCPSYS |
2 | =============== | |
3 | ||
4 | The System Control Processor System (SCPSYS) has several power management | |
5 | related tasks in the system. The tasks include thermal measurement, dynamic | |
6 | voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control. | |
7 | The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power | |
8 | domain control. | |
9 | ||
10 | The driver implements the Generic PM domain bindings described in | |
11 | power/power_domain.txt. It provides the power domains defined in | |
12 | include/dt-bindings/power/mt8173-power.h. | |
13 | ||
14 | Required properties: | |
15 | - compatible: Must be "mediatek,mt8173-scpsys" | |
16 | - #power-domain-cells: Must be 1 | |
17 | - reg: Address range of the SCPSYS unit | |
18 | - infracfg: must contain a phandle to the infracfg controller | |
19 | - clock, clock-names: clocks according to the common clock binding. | |
2a4599a5 JL |
20 | The clocks needed "mm", "mfg", "venc" and "venc_lt". |
21 | These are the clocks which hardware needs to be enabled | |
22 | before enabling certain power domains. | |
859e4280 SH |
23 | |
24 | Example: | |
25 | ||
26 | scpsys: scpsys@10006000 { | |
27 | #power-domain-cells = <1>; | |
28 | compatible = "mediatek,mt8173-scpsys"; | |
29 | reg = <0 0x10006000 0 0x1000>; | |
30 | infracfg = <&infracfg>; | |
31 | clocks = <&clk26m>, | |
32 | <&topckgen CLK_TOP_MM_SEL>; | |
2a4599a5 JL |
33 | <&topckgen CLK_TOP_VENC_SEL>, |
34 | <&topckgen CLK_TOP_VENC_LT_SEL>; | |
35 | clock-names = "mfg", "mm", "venc", "venc_lt"; | |
859e4280 SH |
36 | }; |
37 | ||
38 | Example consumer: | |
39 | ||
40 | afe: mt8173-afe-pcm@11220000 { | |
41 | compatible = "mediatek,mt8173-afe-pcm"; | |
42 | power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; | |
43 | }; |