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1Freescale Enhanced Serial Audio Interface (ESAI) Controller
2
3The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
4for serial communication with a variety of serial devices, including industry
5standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
6other DSPs. It has up to six transmitters and four receivers.
7
8Required properties:
9
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10 - compatible : Compatible list, must contain "fsl,imx35-esai" or
11 "fsl,vf610-esai"
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73a2cd91 13 - reg : Offset and length of the register set for the device.
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73a2cd91 15 - interrupts : Contains the spdif interrupt.
43d24e76 16
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17 - dmas : Generic dma devicetree binding as described in
18 Documentation/devicetree/bindings/dma/dma.txt.
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73a2cd91 20 - dma-names : Two dmas have to be defined, "tx" and "rx".
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73a2cd91 22 - clocks : Contains an entry for each entry in clock-names.
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24 - clock-names : Includes the following entries:
25 "core" The core clock used to access registers
26 "extal" The esai baud clock for esai controller used to
27 derive HCK, SCK and FS.
28 "fsys" The system clock derived from ahb clock used to
29 derive HCK, SCK and FS.
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30 "spba" The spba clock is required when ESAI is placed as a
31 bus slave of the Shared Peripheral Bus and when two
32 or more bus masters (CPU, DMA or DSP) try to access
33 it. This property is optional depending on the SoC
34 design.
43d24e76 35
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36 - fsl,fifo-depth : The number of elements in the transmit and receive
37 FIFOs. This number is the maximum allowed value for
38 TFCR[TFWM] or RFCR[RFWM].
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39
40 - fsl,esai-synchronous: This is a boolean property. If present, indicating
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41 that ESAI would work in the synchronous mode, which
42 means all the settings for Receiving would be
43 duplicated from Transmition related registers.
43d24e76 44
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45 - big-endian : If this property is absent, the native endian mode
46 will be in use as default, or the big endian mode
47 will be in use for all the device registers.
eaba603f 48
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49Example:
50
48c926cd 51esai: esai@2024000 {
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52 compatible = "fsl,imx35-esai";
53 reg = <0x02024000 0x4000>;
54 interrupts = <0 51 0x04>;
55 clocks = <&clks 208>, <&clks 118>, <&clks 208>;
56 clock-names = "core", "extal", "fsys";
57 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
58 dma-names = "rx", "tx";
59 fsl,fifo-depth = <128>;
60 fsl,esai-synchronous;
eaba603f 61 big-endian;
43d24e76 62};