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Commit | Line | Data |
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b6344859 XL |
1 | Freescale Synchronous Audio Interface (SAI). |
2 | ||
3 | The SAI is based on I2S module that used communicating with audio codecs, | |
4 | which provides a synchronous audio interface that supports fullduplex | |
5 | serial interfaces with frame synchronization such as I2S, AC97, TDM, and | |
6 | codec/DSP interfaces. | |
7 | ||
8 | ||
9 | Required properties: | |
c7540644 | 10 | - compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai". |
b6344859 XL |
11 | - reg: Offset and length of the register set for the device. |
12 | - clocks: Must contain an entry for each entry in clock-names. | |
ca3e35c7 NC |
13 | - clock-names : Must include the "bus" for register access and "mclk1" "mclk2" |
14 | "mclk3" for bit clock and frame clock providing. | |
b6344859 XL |
15 | - dmas : Generic dma devicetree binding as described in |
16 | Documentation/devicetree/bindings/dma/dma.txt. | |
17 | - dma-names : Two dmas have to be defined, "tx" and "rx". | |
18 | - pinctrl-names: Must contain a "default" entry. | |
19 | - pinctrl-NNN: One property must exist for each entry in pinctrl-names. | |
20 | See ../pinctrl/pinctrl-bindings.txt for details of the property values. | |
014fd22e XL |
21 | - big-endian: Boolean property, required if all the FTM_PWM registers |
22 | are big-endian rather than little-endian. | |
eadb0019 XL |
23 | - lsb-first: Configures whether the LSB or the MSB is transmitted first for |
24 | the fifo data. If this property is absent, the MSB is transmitted first as | |
25 | default, or the LSB is transmitted first. | |
08fdf65e NC |
26 | - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating |
27 | that SAI will work in the synchronous mode (sync Tx with Rx) which means | |
28 | both the transimitter and receiver will send and receive data by following | |
29 | receiver's bit clocks and frame sync clocks. | |
30 | - fsl,sai-asynchronous: This is a boolean property. If present, indicating | |
31 | that SAI will work in the asynchronous mode, which means both transimitter | |
32 | and receiver will send and receive data by following their own bit clocks | |
33 | and frame sync clocks separately. | |
34 | ||
35 | Note: | |
36 | - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the | |
37 | default synchronous mode (sync Rx with Tx) will be used, which means both | |
38 | transimitter and receiver will send and receive data by following clocks | |
39 | of transimitter. | |
ce7344a4 | 40 | - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. |
b6344859 XL |
41 | |
42 | Example: | |
43 | sai2: sai@40031000 { | |
44 | compatible = "fsl,vf610-sai"; | |
45 | reg = <0x40031000 0x1000>; | |
46 | pinctrl-names = "default"; | |
47 | pinctrl-0 = <&pinctrl_sai2_1>; | |
ca3e35c7 NC |
48 | clocks = <&clks VF610_CLK_PLATFORM_BUS>, |
49 | <&clks VF610_CLK_SAI2>, | |
50 | <&clks 0>, <&clks 0>; | |
51 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
b6344859 XL |
52 | dma-names = "tx", "rx"; |
53 | dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, | |
54 | <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; | |
014fd22e | 55 | big-endian; |
eadb0019 | 56 | lsb-first; |
b6344859 | 57 | }; |