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Commit | Line | Data |
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8020e1bb MC |
1 | Allwinner Sony/Philips Digital Interface Format (S/PDIF) Controller |
2 | ||
3 | The Allwinner S/PDIF audio block is a transceiver that allows the | |
4 | processor to receive and transmit digital audio via an coaxial cable or | |
5 | a fibre cable. | |
6 | For now only playback is supported. | |
7 | ||
8 | Required properties: | |
9 | ||
10 | - compatible : should be one of the following: | |
11 | - "allwinner,sun4i-a10-spdif": for the Allwinner A10 SoC | |
fbb016a2 | 12 | - "allwinner,sun6i-a31-spdif": for the Allwinner A31 SoC |
cb5c978f | 13 | - "allwinner,sun8i-h3-spdif": for the Allwinner H3 SoC |
8020e1bb MC |
14 | |
15 | - reg : Offset and length of the register set for the device. | |
16 | ||
17 | - interrupts : Contains the spdif interrupt. | |
18 | ||
19 | - dmas : Generic dma devicetree binding as described in | |
20 | Documentation/devicetree/bindings/dma/dma.txt. | |
21 | ||
22 | - dma-names : Two dmas have to be defined, "tx" and "rx". | |
23 | ||
24 | - clocks : Contains an entry for each entry in clock-names. | |
25 | ||
26 | - clock-names : Includes the following entries: | |
27 | "apb" clock for the spdif bus. | |
28 | "spdif" clock for spdif controller. | |
29 | ||
fbb016a2 MC |
30 | - resets : reset specifier for the ahb reset (A31 and newer only) |
31 | ||
8020e1bb MC |
32 | Example: |
33 | ||
34 | spdif: spdif@01c21000 { | |
35 | compatible = "allwinner,sun4i-a10-spdif"; | |
36 | reg = <0x01c21000 0x40>; | |
37 | interrupts = <13>; | |
38 | clocks = <&apb0_gates 1>, <&spdif_clk>; | |
39 | clock-names = "apb", "spdif"; | |
40 | dmas = <&dma 0 2>, <&dma 0 2>; | |
41 | dma-names = "rx", "tx"; | |
42 | status = "okay"; | |
43 | }; |