]>
Commit | Line | Data |
---|---|---|
dc4dc360 LD |
1 | NVIDIA Tegra20/Tegra30 SLINK controller. |
2 | ||
3 | Required properties: | |
4 | - compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink". | |
5 | - reg: Should contain SLINK registers location and length. | |
6 | - interrupts: Should contain SLINK interrupts. | |
7 | - nvidia,dma-request-selector : The Tegra DMA controller's phandle and | |
8 | request selector for this SLINK controller. | |
d8f64797 SW |
9 | - clocks : Must contain one entry, for the module clock. |
10 | See ../clocks/clock-bindings.txt for details. | |
07999587 SW |
11 | - resets : Must contain an entry for each entry in reset-names. |
12 | See ../reset/reset.txt for details. | |
13 | - reset-names : Must include the following entries: | |
14 | - spi | |
dc4dc360 LD |
15 | |
16 | Recommended properties: | |
17 | - spi-max-frequency: Definition as per | |
18 | Documentation/devicetree/bindings/spi/spi-bus.txt | |
19 | ||
20 | Example: | |
21 | ||
6a791313 | 22 | spi@7000d600 { |
dc4dc360 LD |
23 | compatible = "nvidia,tegra20-slink"; |
24 | reg = <0x7000d600 0x200>; | |
25 | interrupts = <0 82 0x04>; | |
26 | nvidia,dma-request-selector = <&apbdma 16>; | |
27 | spi-max-frequency = <25000000>; | |
28 | #address-cells = <1>; | |
29 | #size-cells = <0>; | |
d8f64797 | 30 | clocks = <&tegra_car 44>; |
07999587 SW |
31 | resets = <&tegra_car 44>; |
32 | reset-names = "spi"; | |
dc4dc360 LD |
33 | status = "disabled"; |
34 | }; |