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Commit | Line | Data |
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cf9c86ef BH |
1 | Renesas MSIOF spi controller |
2 | ||
3 | Required properties: | |
4286db84 | 4 | - compatible : "renesas,msiof-r8a7790" (R-Car H2) |
e221cc99 GU |
5 | "renesas,msiof-r8a7791" (R-Car M2-W) |
6 | "renesas,msiof-r8a7792" (R-Car V2H) | |
7 | "renesas,msiof-r8a7793" (R-Car M2-N) | |
8 | "renesas,msiof-r8a7794" (R-Car E2) | |
eb51cffa | 9 | "renesas,msiof-r8a7796" (R-Car M3-W) |
ec7f9eb4 | 10 | "renesas,msiof-sh73a0" (SH-Mobile AG5) |
4286db84 SH |
11 | "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device) |
12 | "renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device) | |
13 | "renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device) | |
14 | "renesas,sh-msiof" (deprecated) | |
15 | ||
16 | When compatible with the generic version, nodes | |
17 | must list the SoC-specific version corresponding | |
18 | to the platform first followed by the generic | |
19 | version. | |
20 | ||
a6be4de6 GU |
21 | - reg : A list of offsets and lengths of the register sets for |
22 | the device. | |
23 | If only one register set is present, it is to be used | |
24 | by both the CPU and the DMA engine. | |
25 | If two register sets are present, the first is to be | |
26 | used by the CPU, and the second is to be used by the | |
27 | DMA engine. | |
32d3b2d1 GU |
28 | - interrupt-parent : The phandle for the interrupt controller that |
29 | services interrupts for this device | |
30 | - interrupts : Interrupt specifier | |
31 | - #address-cells : Must be <1> | |
32 | - #size-cells : Must be <0> | |
cf9c86ef BH |
33 | |
34 | Optional properties: | |
32d3b2d1 GU |
35 | - clocks : Must contain a reference to the functional clock. |
36 | - num-cs : Total number of chip-selects (default is 1) | |
a6be4de6 GU |
37 | - dmas : Must contain a list of two references to DMA |
38 | specifiers, one for transmission, and one for | |
39 | reception. | |
40 | - dma-names : Must contain a list of two DMA names, "tx" and "rx". | |
3110628d YS |
41 | - renesas,dtdl : delay sync signal (setup) in transmit mode. |
42 | Must contain one of the following values: | |
43 | 0 (no bit delay) | |
44 | 50 (0.5-clock-cycle delay) | |
45 | 100 (1-clock-cycle delay) | |
46 | 150 (1.5-clock-cycle delay) | |
47 | 200 (2-clock-cycle delay) | |
48 | ||
49 | - renesas,syncdl : delay sync signal (hold) in transmit mode. | |
50 | Must contain one of the following values: | |
51 | 0 (no bit delay) | |
52 | 50 (0.5-clock-cycle delay) | |
53 | 100 (1-clock-cycle delay) | |
54 | 150 (1.5-clock-cycle delay) | |
55 | 200 (2-clock-cycle delay) | |
56 | 300 (3-clock-cycle delay) | |
beb74bb0 GU |
57 | |
58 | Optional properties, deprecated for soctype-specific bindings: | |
32d3b2d1 GU |
59 | - renesas,tx-fifo-size : Overrides the default tx fifo size given in words |
60 | (default is 64) | |
61 | - renesas,rx-fifo-size : Overrides the default rx fifo size given in words | |
eb8d0ac4 | 62 | (default is 64) |
32d3b2d1 GU |
63 | |
64 | Pinctrl properties might be needed, too. See | |
65 | Documentation/devicetree/bindings/pinctrl/renesas,*. | |
beb74bb0 GU |
66 | |
67 | Example: | |
68 | ||
69 | msiof0: spi@e6e20000 { | |
4286db84 SH |
70 | compatible = "renesas,msiof-r8a7791", |
71 | "renesas,rcar-gen2-msiof"; | |
cb6d08a2 | 72 | reg = <0 0xe6e20000 0 0x0064>; |
beb74bb0 GU |
73 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
74 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | |
a6be4de6 GU |
75 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
76 | dma-names = "tx", "rx"; | |
beb74bb0 GU |
77 | #address-cells = <1>; |
78 | #size-cells = <0>; | |
79 | status = "disabled"; | |
80 | }; |