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164c05f0 SS |
1 | # SPDX-License-Identifier: GPL-2.0-only |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface | |
8 | ||
9 | maintainers: | |
10 | - Mark Brown <broonie@kernel.org> | |
11 | ||
12 | allOf: | |
13 | - $ref: "spi-controller.yaml#" | |
14 | - if: | |
15 | properties: | |
16 | compatible: | |
17 | contains: | |
18 | enum: | |
19 | - mscc,ocelot-spi | |
20 | - mscc,jaguar2-spi | |
21 | then: | |
22 | properties: | |
23 | reg: | |
24 | minItems: 2 | |
ca4e2ac2 SS |
25 | - if: |
26 | properties: | |
27 | compatible: | |
28 | contains: | |
29 | enum: | |
30 | - baikal,bt1-sys-ssi | |
31 | then: | |
32 | properties: | |
33 | mux-controls: | |
34 | maxItems: 1 | |
35 | required: | |
36 | - mux-controls | |
37 | else: | |
38 | required: | |
39 | - interrupts | |
164c05f0 SS |
40 | |
41 | properties: | |
42 | compatible: | |
43 | oneOf: | |
44 | - description: Generic DW SPI Controller | |
45 | enum: | |
46 | - snps,dw-apb-ssi | |
47 | - snps,dwc-ssi-1.01a | |
48 | - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller | |
49 | items: | |
50 | - enum: | |
51 | - mscc,ocelot-spi | |
52 | - mscc,jaguar2-spi | |
53 | - const: snps,dw-apb-ssi | |
5ce78f44 LP |
54 | - description: Microchip Sparx5 SoC SPI Controller |
55 | const: microchip,sparx5-spi | |
164c05f0 SS |
56 | - description: Amazon Alpine SPI Controller |
57 | const: amazon,alpine-dw-apb-ssi | |
58 | - description: Renesas RZ/N1 SPI Controller | |
59 | items: | |
60 | - const: renesas,rzn1-spi | |
61 | - const: snps,dw-apb-ssi | |
62 | - description: Intel Keem Bay SPI Controller | |
63 | const: intel,keembay-ssi | |
ca4e2ac2 SS |
64 | - description: Baikal-T1 SPI Controller |
65 | const: baikal,bt1-ssi | |
66 | - description: Baikal-T1 System Boot SPI Controller | |
67 | const: baikal,bt1-sys-ssi | |
7b14a272 DLM |
68 | - description: Canaan Kendryte K210 SoS SPI Controller |
69 | const: canaan,k210-spi | |
164c05f0 SS |
70 | |
71 | reg: | |
72 | minItems: 1 | |
73 | items: | |
74 | - description: DW APB SSI controller memory mapped registers | |
ca4e2ac2 | 75 | - description: SPI MST region map or directly mapped SPI ROM |
164c05f0 SS |
76 | |
77 | interrupts: | |
78 | maxItems: 1 | |
79 | ||
80 | clocks: | |
81 | minItems: 1 | |
82 | items: | |
83 | - description: SPI Controller reference clock source | |
84 | - description: APB interface clock source | |
85 | ||
86 | clock-names: | |
87 | minItems: 1 | |
88 | items: | |
89 | - const: ssi_clk | |
90 | - const: pclk | |
91 | ||
92 | resets: | |
93 | maxItems: 1 | |
94 | ||
95 | reset-names: | |
96 | const: spi | |
97 | ||
98 | reg-io-width: | |
99 | $ref: /schemas/types.yaml#/definitions/uint32 | |
100 | description: I/O register width (in bytes) implemented by this device | |
101 | default: 4 | |
102 | enum: [ 2, 4 ] | |
103 | ||
104 | num-cs: | |
105 | default: 4 | |
106 | minimum: 1 | |
107 | maximum: 4 | |
108 | ||
109 | dmas: | |
110 | items: | |
111 | - description: TX DMA Channel | |
112 | - description: RX DMA Channel | |
113 | ||
114 | dma-names: | |
115 | items: | |
116 | - const: tx | |
117 | - const: rx | |
118 | ||
5ce78f44 LP |
119 | rx-sample-delay-ns: |
120 | default: 0 | |
121 | description: Default value of the rx-sample-delay-ns property. | |
122 | This value will be used if the property is not explicitly defined | |
123 | for a SPI slave device. See below. | |
124 | ||
164c05f0 SS |
125 | patternProperties: |
126 | "^.*@[0-9a-f]+$": | |
127 | type: object | |
128 | properties: | |
129 | reg: | |
130 | minimum: 0 | |
131 | maximum: 3 | |
132 | ||
133 | spi-rx-bus-width: | |
134 | const: 1 | |
135 | ||
136 | spi-tx-bus-width: | |
137 | const: 1 | |
138 | ||
5ce78f44 LP |
139 | rx-sample-delay-ns: |
140 | description: SPI Rx sample delay offset, unit is nanoseconds. | |
141 | The delay from the default sample time before the actual | |
142 | sample of the rxd input signal occurs. The "rx_sample_delay" | |
143 | is an optional feature of the designware controller, and the | |
144 | upper limit is also subject to controller configuration. | |
145 | ||
164c05f0 SS |
146 | unevaluatedProperties: false |
147 | ||
148 | required: | |
149 | - compatible | |
150 | - reg | |
151 | - "#address-cells" | |
152 | - "#size-cells" | |
164c05f0 SS |
153 | - clocks |
154 | ||
155 | examples: | |
156 | - | | |
157 | spi@fff00000 { | |
158 | compatible = "snps,dw-apb-ssi"; | |
159 | reg = <0xfff00000 0x1000>; | |
160 | #address-cells = <1>; | |
161 | #size-cells = <0>; | |
162 | interrupts = <0 154 4>; | |
163 | clocks = <&spi_m_clk>; | |
164 | num-cs = <2>; | |
165 | cs-gpios = <&gpio0 13 0>, | |
166 | <&gpio0 14 0>; | |
5ce78f44 LP |
167 | rx-sample-delay-ns = <3>; |
168 | spi-flash@1 { | |
169 | compatible = "spi-nand"; | |
170 | reg = <1>; | |
171 | rx-sample-delay-ns = <7>; | |
172 | }; | |
164c05f0 | 173 | }; |
ca4e2ac2 SS |
174 | - | |
175 | spi@1f040100 { | |
176 | compatible = "baikal,bt1-sys-ssi"; | |
177 | reg = <0x1f040100 0x900>, | |
178 | <0x1c000000 0x1000000>; | |
179 | #address-cells = <1>; | |
180 | #size-cells = <0>; | |
181 | mux-controls = <&boot_mux>; | |
182 | clocks = <&ccu_sys>; | |
183 | clock-names = "ssi_clk"; | |
184 | }; | |
164c05f0 | 185 | ... |