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Commit | Line | Data |
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1642e662 SRT |
1 | * Universal Flash Storage (UFS) Host Controller |
2 | ||
3 | UFSHC nodes are defined to describe on-chip UFS host controllers. | |
4 | Each UFS controller instance should have its own node. | |
5 | ||
6 | Required properties: | |
47555a5c YG |
7 | - compatible : must contain "jedec,ufs-1.1", may also list one or more |
8 | of the following: | |
9 | "qcom,msm8994-ufshc" | |
10 | "qcom,msm8996-ufshc" | |
11 | "qcom,ufshc" | |
1642e662 SRT |
12 | - interrupts : <interrupt mapping for UFS host controller IRQ> |
13 | - reg : <registers mapping> | |
14 | ||
aa497613 | 15 | Optional properties: |
47555a5c YG |
16 | - phys : phandle to UFS PHY node |
17 | - phy-names : the string "ufsphy" when is found in a node, along | |
18 | with "phys" attribute, provides phandle to UFS PHY node | |
6a771a65 | 19 | - vdd-hba-supply : phandle to UFS host controller supply regulator node |
aa497613 SRT |
20 | - vcc-supply : phandle to VCC supply regulator node |
21 | - vccq-supply : phandle to VCCQ supply regulator node | |
22 | - vccq2-supply : phandle to VCCQ2 supply regulator node | |
23 | - vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V | |
24 | or 2.7-3.6V. This boolean property when set, specifies | |
25 | to use low voltage range of 1.7-1.95V. Note for external | |
26 | UFS cards this property is invalid and valid VCC range is | |
27 | always 2.7-3.6V. | |
28 | - vcc-max-microamp : specifies max. load that can be drawn from vcc supply | |
29 | - vccq-max-microamp : specifies max. load that can be drawn from vccq supply | |
30 | - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply | |
6a771a65 | 31 | - <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator |
aa497613 | 32 | |
c6e79dac SRT |
33 | - clocks : List of phandle and clock specifier pairs |
34 | - clock-names : List of clock input name strings sorted in the same | |
35 | order as the clocks property. | |
4cff6d99 ST |
36 | - freq-table-hz : Array of <min max> operating frequencies stored in the same |
37 | order as the clocks property. If this property is not | |
38 | defined or a value in the array is "0" then it is assumed | |
39 | that the frequency is set by the parent clock or a | |
40 | fixed rate clock source. | |
c6e79dac | 41 | |
aa497613 | 42 | Note: If above properties are not defined it can be assumed that the supply |
c6e79dac | 43 | regulators or clocks are always on. |
aa497613 | 44 | |
1642e662 SRT |
45 | Example: |
46 | ufshc@0xfc598000 { | |
47 | compatible = "jedec,ufs-1.1"; | |
48 | reg = <0xfc598000 0x800>; | |
49 | interrupts = <0 28 0>; | |
aa497613 | 50 | |
6a771a65 RS |
51 | vdd-hba-supply = <&xxx_reg0>; |
52 | vdd-hba-fixed-regulator; | |
aa497613 SRT |
53 | vcc-supply = <&xxx_reg1>; |
54 | vcc-supply-1p8; | |
55 | vccq-supply = <&xxx_reg2>; | |
56 | vccq2-supply = <&xxx_reg3>; | |
57 | vcc-max-microamp = 500000; | |
58 | vccq-max-microamp = 200000; | |
59 | vccq2-max-microamp = 200000; | |
c6e79dac SRT |
60 | |
61 | clocks = <&core 0>, <&ref 0>, <&iface 0>; | |
62 | clock-names = "core_clk", "ref_clk", "iface_clk"; | |
4cff6d99 | 63 | freq-table-hz = <100000000 200000000>, <0 0>, <0 0>; |
47555a5c YG |
64 | phys = <&ufsphy1>; |
65 | phy-names = "ufsphy"; | |
1642e662 | 66 | }; |