]>
Commit | Line | Data |
---|---|---|
d7d30c91 AT |
1 | * USB2 ChipIdea USB controller for ci13xxx |
2 | ||
3 | Required properties: | |
9d062b9b RH |
4 | - compatible: should be one of: |
5 | "fsl,imx27-usb" | |
6 | "lsi,zevio-usb" | |
7 | "qcom,ci-hdrc" | |
8 | "chipidea,usb2" | |
d7d30c91 AT |
9 | - reg: base address and length of the registers |
10 | - interrupts: interrupt for the USB controller | |
11 | ||
9d062b9b RH |
12 | Recommended properies: |
13 | - phy_type: the type of the phy connected to the core. Should be one | |
14 | of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this | |
15 | property the PORTSC register won't be touched. | |
16 | - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" | |
17 | ||
18 | Deprecated properties: | |
19 | - usb-phy: phandle for the PHY device. Use "phys" instead. | |
20 | - fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead. | |
21 | ||
d7d30c91 AT |
22 | Optional properties: |
23 | - clocks: reference to the USB clock | |
24 | - phys: reference to the USB PHY | |
25 | - phy-names: should be "usb-phy" | |
26 | - vbus-supply: reference to the VBUS regulator | |
9d062b9b RH |
27 | - maximum-speed: limit the maximum connection speed to "full-speed". |
28 | - tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts | |
29 | - fsl,usbmisc: (FSL only) phandler of non-core register device, with one | |
30 | argument that indicate usb controller index | |
31 | - disable-over-current: (FSL only) disable over current detect | |
32 | - external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus | |
1bd57127 PC |
33 | - itc-setting: interrupt threshold control register control, the setting |
34 | should be aligned with ITC bits at register USBCMD. | |
c6fba7b7 PC |
35 | - ahb-burst-config: it is vendor dependent, the required value should be |
36 | aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This | |
37 | property is used to change AHB burst configuration, check the chipidea | |
38 | spec for meaning of each value. If this property is not existed, it | |
39 | will use the reset value. | |
bd6e9d11 PC |
40 | - tx-burst-size-dword: it is vendor dependent, the tx burst size in dword |
41 | (4 bytes), This register represents the maximum length of a the burst | |
42 | in 32-bit words while moving data from system memory to the USB | |
43 | bus, changing this value takes effect only the SBUSCFG.AHBBRST is 0. | |
44 | - rx-burst-size-dword: it is vendor dependent, the rx burst size in dword | |
45 | (4 bytes), This register represents the maximum length of a the burst | |
46 | in 32-bit words while moving data from the USB bus to system memory, | |
47 | changing this value takes effect only the SBUSCFG.AHBBRST is 0. | |
d7d30c91 AT |
48 | |
49 | Example: | |
50 | ||
51 | usb@f7ed0000 { | |
52 | compatible = "chipidea,usb2"; | |
53 | reg = <0xf7ed0000 0x10000>; | |
54 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
55 | clocks = <&chip CLKID_USB0>; | |
56 | phys = <&usb_phy0>; | |
57 | phy-names = "usb-phy"; | |
58 | vbus-supply = <®_usb0_vbus>; | |
1bd57127 | 59 | gadget-itc-setting = <0x4>; /* 4 micro-frames */ |
c6fba7b7 PC |
60 | /* Incremental burst of unspecified length */ |
61 | ahb-burst-config = <0x0>; | |
bd6e9d11 PC |
62 | tx-burst-size-dword = <0x10>; /* 64 bytes */ |
63 | rx-burst-size-dword = <0x10>; | |
d7d30c91 | 64 | }; |