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[mirror_ubuntu-artful-kernel.git] / Documentation / devicetree / bindings / usb / dwc3.txt
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1synopsys DWC3 CORE
2
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3DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
4 as described in 'usb/generic.txt'
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5
6Required properties:
22a5aa17 7 - compatible: must be "snps,dwc3"
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8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
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10
11Optional properties:
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12 - usb-phy : array of phandle for the PHY device. The first element
13 in the array is expected to be a handle to the USB2/HS PHY and
14 the second element is expected to be a handle to the USB3/SS PHY
57303488 15 - phys: from the *Generic PHY* bindings
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16 - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
17 or "usb3-phy".
eac68e8f 18 - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
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19 - snps,disable_scramble_quirk: true when SW should disable data scrambling.
20 Only really useful for FPGA builds.
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21 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
22 - snps,lpm-nyet-threshold: LPM NYET threshold
9a5b2f31 23 - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
b5a65c40 24 - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
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25 - snps,req_p1p2p3_quirk: when set, the core will always request for
26 P1/P2/P3 transition sequence.
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27 - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
28 amount of 8B10B errors occur.
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29 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
30 from P0 to P1/P2/P3.
fb67afca 31 - snps,lfps_filter_quirk: when set core will filter LFPS reception.
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32 - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
33 Polling LFPS after RX.Detect.
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34 - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
35 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
36 LTSSM during USB3 Compliance mode.
59acfa20 37 - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
0effe0a3 38 - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
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39 - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG,
40 disabling the suspend signal to the PHY.
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41 - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
42 in PHY P3 power state.
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43 - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists
44 in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
45 a free-running PHY clock.
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46 - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power
47 from P0 to P1/P2/P3 without delay.
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48 - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
49 during HS transmit.
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50 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
51 utmi_l1_suspend_n, false when asserts utmi_sleep_n
52 - snps,hird-threshold: HIRD threshold
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53 - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
54 UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
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55 - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
56 register for post-silicon frame length adjustment when the
57 fladj_30mhz_sdbnd signal is invalid or incorrect.
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59 - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
60
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61 - in addition all properties from usb-xhci.txt from the current directory are
62 supported as well
63
64
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65This is usually a subnode to DWC3 glue to which it is connected.
66
67dwc3@4a030000 {
22a5aa17 68 compatible = "snps,dwc3";
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69 reg = <0x4a030000 0xcfff>;
70 interrupts = <0 92 4>
71 usb-phy = <&usb2_phy>, <&usb3,phy>;
5088b6f5 72};