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76bf85cc WW |
1 | Rockchip SuperSpeed DWC3 USB SoC controller |
2 | ||
3 | Required properties: | |
4 | - compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC | |
5 | - clocks: A list of phandle + clock-specifier pairs for the | |
6 | clocks listed in clock-names | |
7 | - clock-names: Should contain the following: | |
8 | "ref_clk" Controller reference clk, have to be 24 MHz | |
9 | "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz | |
10 | "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS | |
11 | operation and >= 30MHz for HS operation | |
12 | "grf_clk" Controller grf clk | |
13 | ||
14 | Required child node: | |
15 | A child node must exist to represent the core DWC3 IP block. The name of | |
16 | the node is not important. The content of the node is defined in dwc3.txt. | |
17 | ||
18 | Phy documentation is provided in the following places: | |
19 | Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt | |
20 | ||
21 | Example device nodes: | |
22 | ||
23 | usbdrd3_0: usb@fe800000 { | |
24 | compatible = "rockchip,rk3399-dwc3"; | |
25 | clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, | |
26 | <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; | |
27 | clock-names = "ref_clk", "suspend_clk", | |
28 | "bus_clk", "grf_clk"; | |
29 | #address-cells = <2>; | |
30 | #size-cells = <2>; | |
31 | ranges; | |
32 | status = "disabled"; | |
33 | usbdrd_dwc3_0: dwc3@fe800000 { | |
34 | compatible = "snps,dwc3"; | |
35 | reg = <0x0 0xfe800000 0x0 0x100000>; | |
36 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
37 | dr_mode = "otg"; | |
38 | status = "disabled"; | |
39 | }; | |
40 | }; | |
41 | ||
42 | usbdrd3_1: usb@fe900000 { | |
43 | compatible = "rockchip,rk3399-dwc3"; | |
44 | clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, | |
45 | <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; | |
46 | clock-names = "ref_clk", "suspend_clk", | |
47 | "bus_clk", "grf_clk"; | |
48 | #address-cells = <2>; | |
49 | #size-cells = <2>; | |
50 | ranges; | |
51 | status = "disabled"; | |
52 | usbdrd_dwc3_1: dwc3@fe900000 { | |
53 | compatible = "snps,dwc3"; | |
54 | reg = <0x0 0xfe900000 0x0 0x100000>; | |
55 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
56 | dr_mode = "otg"; | |
57 | status = "disabled"; | |
58 | }; | |
59 | }; |